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Merge pull request #404 from CodeConstruct:dev/gpio-interrupt
Interrupts for GPIO Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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@@ -14,6 +14,7 @@
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#define XICS_ICP_BASE 0xc0004000 /* Interrupt controller */
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#define XICS_ICS_BASE 0xc0005000 /* Interrupt controller */
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#define SPI_FCTRL_BASE 0xc0006000 /* SPI flash controller registers */
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#define GPIO_BASE 0xc0007000 /* GPIO registers */
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#define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */
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#define LETH_CSR_BASE 0xc8020000 /* LiteEth CSR registers */
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#define LETH_SRAM_BASE 0xc8030000 /* LiteEth MMIO space */
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@@ -26,6 +27,9 @@
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*/
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#define IRQ_UART0 0
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#define IRQ_ETHERNET 1
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#define IRQ_UART1 2
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#define IRQ_SDCARD 3
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#define IRQ_GPIO 4
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/*
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* Register definitions for the syscon registers
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@@ -156,5 +160,20 @@
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#define SPI_REG_AUTO_CFG_CSTOUT_SHIFT 24 /* CS timeout */
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#define SPI_REG_AUTO_CFG_CSTOUT_MASK (0x3f << SPI_REG_AUTO_CFG_CSTOUT_SHIFT)
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/*
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* Register definitions for GPIO
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*/
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#define GPIO_REG_DATA_OUT 0x00
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#define GPIO_REG_DATA_IN 0x04
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#define GPIO_REG_DIR 0x08
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#define GPIO_REG_DATA_SET 0x10
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#define GPIO_REG_DATA_CLR 0x14
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#define GPIO_REG_INT_EN 0x20
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#define GPIO_REG_INT_STAT 0x24
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#define GPIO_REG_INT_CLR 0x30
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#define GPIO_REG_INT_TYPE 0x34
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#define GPIO_REG_INT_BOTH_EDGE 0x38
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#define GPIO_REG_INT_LEVEL 0x3C
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#endif /* __MICROWATT_SOC_H */
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