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Explicitly check against '1' in if statements

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nvc doesn't like what I think is a VHDL 2008 construct. Lets just
check against '1' explicitly.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2019-09-12 09:19:31 +10:00 committed by Anton Blanchard
parent 8b88e26ece
commit b9e28598b4
2 changed files with 2 additions and 2 deletions
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2
decode1.vhdl
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@ -248,7 +248,7 @@ begin
ppc_insn := PPC_ILLEGAL;
if f_in.valid then
if f_in.valid = '1' then
v.nia := f_in.nia;
v.insn := f_in.insn;

2
decode2.vhdl
View File

@ -260,7 +260,7 @@ begin
v.e.cr := c_in.read_cr_data;
v.e.input_carry := d_in.decode.input_carry;
v.e.output_carry := d_in.decode.output_carry;
if d_in.decode.lr then
if d_in.decode.lr = '1' then
v.e.lr := insn_lk(d_in.insn);
end if;
v.e.const1 := decode_const_a(d_in.decode.const_a, d_in.insn);