loadstore1: Ensure tlbie instructions get completed

Since commit c938246cc8f3 ("dcache: Simplify addressing of the dcache
TLB", 2025-04-05), tlbie instructions have been sent down the
loadstore pipe with both req.dc_req and req.mmu_op set, so that the
tlbie gets sent both to the data cache and the MMU.  This is so that
the relevant TLB hit signals are set correctly in the dcache for a
single-page invalidation.  However, this means that loadstore1 was not
sending a completion to writeback for the tlbie.  Normally this
doesn't cause a problem, but if the tlbie is followed by an
instruction that is marked 'single-pipe' in the decode1 tables, such
as sync (any variant), decode2 will then stall forever waiting for the
tlbie to complete before issuing the following instruction.

To fix this, clear req.dc_req in the second loadstore stage for a
tlbie (actually for any MMU operation, but tlbie is the only
instruction that would have dc_req set).

Fixes: c938246cc8f3 ("dcache: Simplify addressing of the dcache TLB", 2025-04-05)
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

loadstore1.vhdl

@@ -951,6 +951,13 @@ begin
                 if r1.req.read_spr = '1' then
                     v.addr0 := sprval;
                 end if;
+                -- tlbie has req.dc_req set in order to send the TLB probe to
+                -- the dcache, but since there is no acknowledgement to wait for,
+                -- clear req.dc_req so that loadstore1_3 completes when the MMU
+                -- is finished.
+                if r1.req.mmu_op = '1' then
+                    v.req.dc_req := '0';
+                end if;
 
                 -- Work out load formatter controls for next cycle
                 for i in 0 to 7 loop