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wishbone_arbiter: Remove early_sel optimization when > 4 masters

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For the sake of overall timing in larger SoCs, remove the early_sel
optimization when there are more than 4 masters.

Also make the ack and stall signals to a particular master depend on
that master's cyc, not on the busy signal, which can depend on any
master's cyc.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras 2025-01-05 20:52:06 +11:00
parent bf55efec6d
commit d1c7b654bb
1 changed files with 9 additions and 5 deletions
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14
wishbone_arbiter.vhdl
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@ -4,7 +4,6 @@ use ieee.std_logic_1164.all;
library work; library work;
use work.wishbone_types.all; use work.wishbone_types.all;
-- TODO: Use an array of master/slaves with parametric size
entity wishbone_arbiter is entity wishbone_arbiter is
generic( generic(
NUM_MASTERS : positive := 3 NUM_MASTERS : positive := 3
@ -28,18 +27,23 @@ begin
busy <= wb_masters_in(selected).cyc; busy <= wb_masters_in(selected).cyc;
wishbone_muxes: process(selected, candidate, busy, wb_slave_in, wb_masters_in) wishbone_muxes: process(all)
variable early_sel : wb_arb_master_t; variable early_sel : wb_arb_master_t;
begin begin
early_sel := selected; early_sel := selected;
if busy = '0' then if NUM_MASTERS <= 4 and busy = '0' then
early_sel := candidate; early_sel := candidate;
end if; end if;
wb_slave_out <= wb_masters_in(early_sel); wb_slave_out <= wb_masters_in(early_sel);
for i in 0 to NUM_MASTERS-1 loop for i in 0 to NUM_MASTERS-1 loop
wb_masters_out(i).dat <= wb_slave_in.dat; wb_masters_out(i).dat <= wb_slave_in.dat;
wb_masters_out(i).ack <= wb_slave_in.ack when early_sel = i else '0'; if early_sel = i and wb_masters_in(i).cyc = '1' then
wb_masters_out(i).stall <= wb_slave_in.stall when early_sel = i else '1'; wb_masters_out(i).ack <= wb_slave_in.ack;
wb_masters_out(i).stall <= wb_slave_in.stall;
else
wb_masters_out(i).ack <= '0';
wb_masters_out(i).stall <= '1';
end if;
end loop; end loop;
end process; end process;