FPU: Clear S in ADD_SHIFT state

Otherwise, if this is a multiply-add instruction and the result needs
to be shifted left, bits of the product in S will contaminate the
final result.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

fpu.vhdl

@@ -1865,6 +1865,7 @@ begin
                 re_set_result <= '1';
                 v.x := s_nz;
                 set_x := '1';
+                set_s := '1';
                 v.longmask := r.single_prec;
                 if r.add_bsmall = '1' then
                     v.state := ADD_2;