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Merge pull request #239 from paulusmack/master

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Implement BE and 32b modes
This commit is contained in:
Michael Neuling 2020-08-27 21:28:21 +10:00 committed by GitHub
commit da4be71bd3
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GPG Key ID: 4AEE18F83AFDEB23
21 changed files with 1147 additions and 52 deletions
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13
common.vhdl
View File

@ -108,6 +108,7 @@ package common is
req: std_ulogic;
virt_mode : std_ulogic;
priv_mode : std_ulogic;
big_endian : std_ulogic;
stop_mark: std_ulogic;
sequential: std_ulogic;
nia: std_ulogic_vector(63 downto 0);
@ -245,10 +246,13 @@ package common is
redirect: std_ulogic;
virt_mode: std_ulogic;
priv_mode: std_ulogic;
big_endian: std_ulogic;
mode_32bit: std_ulogic;
redirect_nia: std_ulogic_vector(63 downto 0);
end record;
constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
priv_mode => '0', others => (others => '0'));
priv_mode => '0', big_endian => '0',
mode_32bit => '0', others => (others => '0'));
type Execute1ToLoadstore1Type is record
valid : std_ulogic;
@ -270,17 +274,19 @@ package common is
rc : std_ulogic; -- set for stcx.
virt_mode : std_ulogic; -- do translation through TLB
priv_mode : std_ulogic; -- privileged mode (MSR[PR] = 0)
mode_32bit : std_ulogic; -- trim addresses to 32 bits
end record;
constant Execute1ToLoadstore1Init : Execute1ToLoadstore1Type := (valid => '0', op => OP_ILLEGAL, ci => '0', byte_reverse => '0',
sign_extend => '0', update => '0', xerc => xerc_init,
reserve => '0', rc => '0', virt_mode => '0', priv_mode => '0',
nia => (others => '0'), insn => (others => '0'),
addr1 => (others => '0'), addr2 => (others => '0'), data => (others => '0'), length => (others => '0'),
others => (others => '0'));
mode_32bit => '0', others => (others => '0'));
type Loadstore1ToExecute1Type is record
busy : std_ulogic;
exception : std_ulogic;
alignment : std_ulogic;
invalid : std_ulogic;
perm_error : std_ulogic;
rc_error : std_ulogic;
@ -373,6 +379,7 @@ package common is
type Execute1ToWritebackType is record
valid: std_ulogic;
rc : std_ulogic;
mode_32bit : std_ulogic;
write_enable : std_ulogic;
write_reg: gspr_index_t;
write_data: std_ulogic_vector(63 downto 0);
@ -385,7 +392,7 @@ package common is
exc_write_reg : gspr_index_t;
exc_write_data : std_ulogic_vector(63 downto 0);
end record;
constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', write_enable => '0',
constant Execute1ToWritebackInit : Execute1ToWritebackType := (valid => '0', rc => '0', mode_32bit => '0', write_enable => '0',
write_cr_enable => '0', exc_write_enable => '0',
write_xerc_enable => '0', xerc => xerc_init,
write_data => (others => '0'), write_cr_mask => (others => '0'),

18
execute1.vhdl
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@ -496,9 +496,11 @@ begin
v.terminate := '0';
icache_inval <= '0';
v.busy := '0';
-- send MSR[IR] and ~MSR[PR] up to fetch1
-- send MSR[IR], ~MSR[PR], ~MSR[LE] and ~MSR[SF] up to fetch1
v.f.virt_mode := ctrl.msr(MSR_IR);
v.f.priv_mode := not ctrl.msr(MSR_PR);
v.f.big_endian := not ctrl.msr(MSR_LE);
v.f.mode_32bit := not ctrl.msr(MSR_SF);
-- Next insn adder used in a couple of places
next_nia := std_ulogic_vector(unsigned(e_in.nia) + 4);
@ -521,6 +523,8 @@ begin
v.last_nia := e_in.nia;
end if;
v.e.mode_32bit := not ctrl.msr(MSR_SF);
if ctrl.irq_state = WRITE_SRR1 then
v.e.exc_write_reg := fast_spr_num(SPR_SRR1);
v.e.exc_write_data := ctrl.srr1;
@ -740,6 +744,8 @@ begin
when OP_RFID =>
v.f.virt_mode := a_in(MSR_IR) or a_in(MSR_PR);
v.f.priv_mode := not a_in(MSR_PR);
v.f.big_endian := not a_in(MSR_LE);
v.f.mode_32bit := not a_in(MSR_SF);
-- Can't use msr_copy here because the partial function MSR
-- bits should be left unchanged, not zeroed.
ctrl_tmp.msr(63 downto 31) <= a_in(63 downto 31);
@ -1133,7 +1139,9 @@ begin
-- generate DSI or DSegI for load/store exceptions
-- or ISI or ISegI for instruction fetch exceptions
if l_in.exception = '1' then
if l_in.instr_fault = '0' then
if l_in.alignment = '1' then
v.f.redirect_nia := std_logic_vector(to_unsigned(16#600#, 64));
elsif l_in.instr_fault = '0' then
if l_in.segment_fault = '0' then
v.f.redirect_nia := std_logic_vector(to_unsigned(16#300#, 64));
else
@ -1161,6 +1169,9 @@ begin
v.f.redirect := '1';
v.f.virt_mode := '0';
v.f.priv_mode := '1';
-- XXX need an interrupt LE bit here, e.g. from LPCR
v.f.big_endian := '0';
v.f.mode_32bit := '0';
end if;
if v.f.redirect = '1' then
@ -1176,7 +1187,7 @@ begin
lv.data := c_in;
lv.write_reg := gspr_to_gpr(e_in.write_reg);
lv.length := e_in.data_len;
lv.byte_reverse := e_in.byte_reverse;
lv.byte_reverse := e_in.byte_reverse xnor ctrl.msr(MSR_LE);
lv.sign_extend := e_in.sign_extend;
lv.update := e_in.update;
lv.update_reg := gspr_to_gpr(e_in.read_reg1);
@ -1191,6 +1202,7 @@ begin
end if;
lv.virt_mode := ctrl.msr(MSR_DR);
lv.priv_mode := not ctrl.msr(MSR_PR);
lv.mode_32bit := not ctrl.msr(MSR_SF);
-- Update registers
rin <= v;

23
fetch1.vhdl
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@ -38,6 +38,7 @@ architecture behaviour of fetch1 is
type stop_state_t is (RUNNING, STOPPED, RESTARTING);
type reg_internal_t is record
stop_state: stop_state_t;
mode_32bit: std_ulogic;
end record;
signal r, r_next : Fetch1ToIcacheType;
signal r_int, r_next_int : reg_internal_t;
@ -50,8 +51,10 @@ begin
log_nia <= r.nia(63) & r.nia(43 downto 2);
if r /= r_next then
report "fetch1 rst:" & std_ulogic'image(rst) &
" IR:" & std_ulogic'image(e_in.virt_mode) &
" P:" & std_ulogic'image(e_in.priv_mode) &
" IR:" & std_ulogic'image(r_next.virt_mode) &
" P:" & std_ulogic'image(r_next.priv_mode) &
" E:" & std_ulogic'image(r_next.big_endian) &
" 32:" & std_ulogic'image(r_next_int.mode_32bit) &
" R:" & std_ulogic'image(e_in.redirect) & std_ulogic'image(d_in.redirect) &
" S:" & std_ulogic'image(stall_in) &
" T:" & std_ulogic'image(stop_in) &
@ -81,13 +84,23 @@ begin
end if;
v.virt_mode := '0';
v.priv_mode := '1';
v.big_endian := '0';
v_int.stop_state := RUNNING;
v_int.mode_32bit := '0';
elsif e_in.redirect = '1' then
v.nia := e_in.redirect_nia(63 downto 2) & "00";
if e_in.mode_32bit = '1' then
v.nia(63 downto 32) := (others => '0');
end if;
v.virt_mode := e_in.virt_mode;
v.priv_mode := e_in.priv_mode;
v.big_endian := e_in.big_endian;
v_int.mode_32bit := e_in.mode_32bit;
elsif d_in.redirect = '1' then
v.nia := d_in.redirect_nia(63 downto 2) & "00";
if r_int.mode_32bit = '1' then
v.nia(63 downto 32) := (others => '0');
end if;
elsif stall_in = '0' then
-- For debug stop/step to work properly we need a little bit of
@ -133,7 +146,11 @@ begin
end case;
if increment then
v.nia := std_logic_vector(unsigned(v.nia) + 4);
if r_int.mode_32bit = '0' then
v.nia := std_ulogic_vector(unsigned(r.nia) + 4);
else
v.nia := x"00000000" & std_ulogic_vector(unsigned(r.nia(31 downto 0)) + 4);
end if;
v.sequential := '1';
end if;
end if;

27
icache.vhdl
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@ -98,7 +98,8 @@ architecture rtl of icache is
-- SET_SIZE_BITS is the log base 2 of the set size
constant SET_SIZE_BITS : natural := LINE_OFF_BITS + INDEX_BITS;
-- TAG_BITS is the number of bits of the tag part of the address
constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS;
-- the +1 is to allow the endianness to be stored in the tag
constant TAG_BITS : natural := REAL_ADDR_BITS - SET_SIZE_BITS + 1;
-- WAY_BITS is the number of bits to select a way
constant WAY_BITS : natural := log2(NUM_WAYS);
@ -289,9 +290,10 @@ architecture rtl of icache is
end;
-- Get the tag value from the address
function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0)) return cache_tag_t is
function get_tag(addr: std_ulogic_vector(REAL_ADDR_BITS - 1 downto 0);
endian: std_ulogic) return cache_tag_t is
begin
return addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
return endian & addr(REAL_ADDR_BITS - 1 downto SET_SIZE_BITS);
end;
-- Read a tag from a tag memory row
@ -327,9 +329,9 @@ begin
report "geometry bits don't add up" severity FAILURE;
assert (LINE_OFF_BITS = ROW_OFF_BITS + ROW_LINEBITS)
report "geometry bits don't add up" severity FAILURE;
assert (REAL_ADDR_BITS = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
assert (REAL_ADDR_BITS + 1 = TAG_BITS + INDEX_BITS + LINE_OFF_BITS)
report "geometry bits don't add up" severity FAILURE;
assert (REAL_ADDR_BITS = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
assert (REAL_ADDR_BITS + 1 = TAG_BITS + ROW_BITS + ROW_OFF_BITS)
report "geometry bits don't add up" severity FAILURE;
sim_debug: if SIM generate
@ -359,6 +361,7 @@ begin
signal wr_addr : std_ulogic_vector(ROW_BITS-1 downto 0);
signal dout : cache_row_t;
signal wr_sel : std_ulogic_vector(ROW_SIZE-1 downto 0);
signal wr_dat : std_ulogic_vector(wishbone_in.dat'left downto 0);
begin
way: entity work.cache_ram
generic map (
@ -372,10 +375,20 @@ begin
rd_data => dout,
wr_sel => wr_sel,
wr_addr => wr_addr,
wr_data => wishbone_in.dat
wr_data => wr_dat
);
process(all)
variable j: integer;
begin
-- byte-swap read data if big endian
if r.store_tag(TAG_BITS - 1) = '0' then
wr_dat <= wishbone_in.dat;
else
for i in 0 to (wishbone_in.dat'length / 8) - 1 loop
j := ((i / 4) * 4) + (3 - (i mod 4));
wr_dat(i * 8 + 7 downto i * 8) <= wishbone_in.dat(j * 8 + 7 downto j * 8);
end loop;
end if;
do_read <= not (stall_in or use_previous);
do_write <= '0';
if wishbone_in.ack = '1' and replace_way = i then
@ -494,7 +507,7 @@ begin
-- Extract line, row and tag from request
req_index <= get_index(i_in.nia);
req_row <= get_row(i_in.nia);
req_tag <= get_tag(real_addr);
req_tag <= get_tag(real_addr, i_in.big_endian);
-- Calculate address of beginning of cache row, will be
-- used for cache miss processing if needed

54
loadstore1.vhdl
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@ -78,12 +78,14 @@ architecture behave of loadstore1 is
dar : std_ulogic_vector(63 downto 0);
dsisr : std_ulogic_vector(31 downto 0);
instr_fault : std_ulogic;
align_intr : std_ulogic;
sprval : std_ulogic_vector(63 downto 0);
busy : std_ulogic;
wait_dcache : std_ulogic;
wait_mmu : std_ulogic;
do_update : std_ulogic;
extra_cycle : std_ulogic;
mode_32bit : std_ulogic;
end record;
type byte_sel_t is array(0 to 7) of std_ulogic;
@ -170,6 +172,7 @@ begin
variable dsisr : std_ulogic_vector(31 downto 0);
variable mmu_mtspr : std_ulogic;
variable itlb_fault : std_ulogic;
variable misaligned : std_ulogic;
begin
v := r;
req := '0';
@ -201,14 +204,20 @@ begin
end loop;
-- Work out the sign bit for sign extension.
-- Assumes we are not doing both sign extension and byte reversal,
-- in that for unaligned loads crossing two dwords we end up
-- using a bit from the second dword, whereas for a byte-reversed
-- (i.e. big-endian) load the sign bit would be in the first dword.
negative := (r.length(3) and data_permuted(63)) or
(r.length(2) and data_permuted(31)) or
(r.length(1) and data_permuted(15)) or
(r.length(0) and data_permuted(7));
-- For unaligned loads crossing two dwords, the sign bit is in the
-- first dword for big-endian (byte_reverse = 1), or the second dword
-- for little-endian.
if r.dwords_done = '1' and r.byte_reverse = '1' then
negative := (r.length(3) and r.load_data(63)) or
(r.length(2) and r.load_data(31)) or
(r.length(1) and r.load_data(15)) or
(r.length(0) and r.load_data(7));
else
negative := (r.length(3) and data_permuted(63)) or
(r.length(2) and data_permuted(31)) or
(r.length(1) and data_permuted(15)) or
(r.length(0) and data_permuted(7));
end if;
-- trim and sign-extend
for i in 0 to 7 loop
@ -266,13 +275,16 @@ begin
exception := '0';
if r.dwords_done = '1' or r.state = SECOND_REQ then
maddr := next_addr;
addr := next_addr;
byte_sel := r.second_bytes;
else
maddr := r.addr;
addr := r.addr;
byte_sel := r.first_bytes;
end if;
addr := maddr;
if r.mode_32bit = '1' then
addr(63 downto 32) := (others => '0');
end if;
maddr := addr;
case r.state is
when IDLE =>
@ -348,6 +360,7 @@ begin
when TLBIE_WAIT =>
when COMPLETE =>
exception := r.align_intr;
end case;
@ -359,10 +372,12 @@ begin
-- Note that l_in.valid is gated with busy inside execute1
if l_in.valid = '1' then
v.addr := lsu_sum;
v.mode_32bit := l_in.mode_32bit;
v.load := '0';
v.dcbz := '0';
v.tlbie := '0';
v.instr_fault := '0';
v.align_intr := '0';
v.dwords_done := '0';
v.last_dword := '1';
v.write_reg := l_in.write_reg;
@ -383,6 +398,9 @@ begin
v.extra_cycle := '0';
addr := lsu_sum;
if l_in.mode_32bit = '1' then
addr(63 downto 32) := (others => '0');
end if;
maddr := l_in.addr2; -- address from RB for tlbie
-- XXX Temporary hack. Mark the op as non-cachable if the address
@ -397,6 +415,10 @@ begin
v.first_bytes := byte_sel;
v.second_bytes := long_sel(15 downto 8);
-- check alignment for larx/stcx
misaligned := or (std_ulogic_vector(unsigned(l_in.length(2 downto 0)) - 1) and addr(2 downto 0));
v.align_intr := l_in.reserve and misaligned;
case l_in.op is
when OP_STORE =>
req := '1';
@ -406,6 +428,7 @@ begin
-- Allow an extra cycle for RA update on loads
v.extra_cycle := l_in.update;
when OP_DCBZ =>
v.align_intr := v.nc;
req := '1';
v.dcbz := '1';
when OP_TLBIE =>
@ -454,7 +477,9 @@ begin
end case;
if req = '1' then
if long_sel(15 downto 8) = "00000000" then
if v.align_intr = '1' then
v.state := COMPLETE;
elsif long_sel(15 downto 8) = "00000000" then
v.state := ACK_WAIT;
else
v.state := SECOND_REQ;
@ -465,7 +490,7 @@ begin
end if;
-- Update outputs to dcache
d_out.valid <= req;
d_out.valid <= req and not v.align_intr;
d_out.load <= v.load;
d_out.dcbz <= v.dcbz;
d_out.nc <= v.nc;
@ -512,6 +537,7 @@ begin
-- update exception info back to execute1
e_out.busy <= busy;
e_out.exception <= exception;
e_out.alignment <= r.align_intr;
e_out.instr_fault <= r.instr_fault;
e_out.invalid <= m_in.invalid;
e_out.badtree <= m_in.badtree;
@ -520,7 +546,7 @@ begin
e_out.segment_fault <= m_in.segerr;
if exception = '1' and r.instr_fault = '0' then
v.dar := addr;
if m_in.segerr = '0' then
if m_in.segerr = '0' and r.align_intr = '0' then
v.dsisr := dsisr;
end if;
end if;

47
tests/mmu/mmu.c
View File

@ -4,8 +4,10 @@
#include "console.h"
#define MSR_LE 0x1
#define MSR_DR 0x10
#define MSR_IR 0x20
#define MSR_SF 0x8000000000000000ul
extern int test_read(long *addr, long *ret, long init);
extern int test_write(long *addr, long val);
@ -445,10 +447,11 @@ int mmu_test_11(void)
unsigned long ptr = 0x523000;
/* this should fail */
if (test_exec(0, ptr, MSR_IR))
if (test_exec(0, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* SRR0 and SRR1 should be set correctly */
if (mfspr(SRR0) != (long) ptr || mfspr(SRR1) != 0x40000020)
if (mfspr(SRR0) != (long) ptr ||
mfspr(SRR1) != (MSR_SF | 0x40000000 | MSR_IR | MSR_LE))
return 2;
return 0;
}
@ -462,12 +465,12 @@ int mmu_test_12(void)
/* create PTE */
map((void *)ptr, (void *)mem, PERM_EX | REF);
/* this should succeed and be a cache miss */
if (!test_exec(0, ptr, MSR_IR))
if (!test_exec(0, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* create a second PTE */
map((void *)ptr2, (void *)mem, PERM_EX | REF);
/* this should succeed and be a cache hit */
if (!test_exec(0, ptr2, MSR_IR))
if (!test_exec(0, ptr2, MSR_SF | MSR_IR | MSR_LE))
return 2;
return 0;
}
@ -481,17 +484,18 @@ int mmu_test_13(void)
/* create a PTE */
map((void *)ptr, (void *)mem, PERM_EX | REF);
/* this should succeed */
if (!test_exec(1, ptr, MSR_IR))
if (!test_exec(1, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* invalidate the PTE */
unmap((void *)ptr);
/* install a second PTE */
map((void *)ptr2, (void *)mem, PERM_EX | REF);
/* this should fail */
if (test_exec(1, ptr, MSR_IR))
if (test_exec(1, ptr, MSR_SF | MSR_IR | MSR_LE))
return 2;
/* SRR0 and SRR1 should be set correctly */
if (mfspr(SRR0) != (long) ptr || mfspr(SRR1) != 0x40000020)
if (mfspr(SRR0) != (long) ptr ||
mfspr(SRR1) != (MSR_SF | 0x40000000 | MSR_IR | MSR_LE))
return 3;
return 0;
}
@ -506,15 +510,16 @@ int mmu_test_14(void)
/* create a PTE */
map((void *)ptr, (void *)mem, PERM_EX | REF);
/* this should fail due to second page not being mapped */
if (test_exec(2, ptr, MSR_IR))
if (test_exec(2, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* SRR0 and SRR1 should be set correctly */
if (mfspr(SRR0) != ptr2 || mfspr(SRR1) != 0x40000020)
if (mfspr(SRR0) != ptr2 ||
mfspr(SRR1) != (MSR_SF | 0x40000000 | MSR_IR | MSR_LE))
return 2;
/* create a PTE for the second page */
map((void *)ptr2, (void *)mem2, PERM_EX | REF);
/* this should succeed */
if (!test_exec(2, ptr, MSR_IR))
if (!test_exec(2, ptr, MSR_SF | MSR_IR | MSR_LE))
return 3;
return 0;
}
@ -527,10 +532,11 @@ int mmu_test_15(void)
/* create a PTE without execute permission */
map((void *)ptr, (void *)mem, DFLT_PERM);
/* this should fail */
if (test_exec(0, ptr, MSR_IR))
if (test_exec(0, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* SRR0 and SRR1 should be set correctly */
if (mfspr(SRR0) != ptr || mfspr(SRR1) != 0x10000020)
if (mfspr(SRR0) != ptr ||
mfspr(SRR1) != (MSR_SF | 0x10000000 | MSR_IR | MSR_LE))
return 2;
return 0;
}
@ -547,15 +553,16 @@ int mmu_test_16(void)
/* create a PTE for the second page without execute permission */
map((void *)ptr2, (void *)mem2, PERM_RD | REF);
/* this should fail due to second page being no-execute */
if (test_exec(2, ptr, MSR_IR))
if (test_exec(2, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* SRR0 and SRR1 should be set correctly */
if (mfspr(SRR0) != ptr2 || mfspr(SRR1) != 0x10000020)
if (mfspr(SRR0) != ptr2 ||
mfspr(SRR1) != (MSR_SF | 0x10000000 | MSR_IR | MSR_LE))
return 2;
/* create a PTE for the second page with execute permission */
map((void *)ptr2, (void *)mem2, PERM_RD | PERM_EX | REF);
/* this should succeed */
if (!test_exec(2, ptr, MSR_IR))
if (!test_exec(2, ptr, MSR_SF | MSR_IR | MSR_LE))
return 3;
return 0;
}
@ -568,20 +575,22 @@ int mmu_test_17(void)
/* create a PTE without the ref bit set */
map((void *)ptr, (void *)mem, PERM_EX);
/* this should fail */
if (test_exec(2, ptr, MSR_IR))
if (test_exec(2, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* SRR0 and SRR1 should be set correctly */
if (mfspr(SRR0) != (long) ptr || mfspr(SRR1) != 0x00040020)
if (mfspr(SRR0) != (long) ptr ||
mfspr(SRR1) != (MSR_SF | 0x00040000 | MSR_IR | MSR_LE))
return 2;
/* create a PTE without ref or execute permission */
unmap((void *)ptr);
map((void *)ptr, (void *)mem, 0);
/* this should fail */
if (test_exec(2, ptr, MSR_IR))
if (test_exec(2, ptr, MSR_SF | MSR_IR | MSR_LE))
return 1;
/* SRR0 and SRR1 should be set correctly */
/* RC update fail bit should not be set */
if (mfspr(SRR0) != (long) ptr || mfspr(SRR1) != 0x10000020)
if (mfspr(SRR0) != (long) ptr ||
mfspr(SRR1) != (MSR_SF | 0x10000000 | MSR_IR | MSR_LE))
return 2;
return 0;
}

3
tests/modes/Makefile Normal file
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TEST=modes
include ../Makefile.test

232
tests/modes/head.S Normal file
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/* Copyright 2013-2014 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Load an immediate 64-bit value into a register */
#define LOAD_IMM64(r, e) \
lis r,(e)@highest; \
ori r,r,(e)@higher; \
rldicr r,r, 32, 31; \
oris r,r, (e)@h; \
ori r,r, (e)@l;
.section ".head","ax"
/*
* Microwatt currently enters in LE mode at 0x0, so we don't need to
* do any endian fix ups
*/
. = 0
.global _start
_start:
LOAD_IMM64(%r10,__bss_start)
LOAD_IMM64(%r11,__bss_end)
subf %r11,%r10,%r11
addi %r11,%r11,63
srdi. %r11,%r11,6
beq 2f
mtctr %r11
1: dcbz 0,%r10
addi %r10,%r10,64
bdnz 1b
2: LOAD_IMM64(%r1,__stack_top)
li %r0,0
stdu %r0,-16(%r1)
mtsprg2 %r0
LOAD_IMM64(%r12, main)
mtctr %r12
bctrl
attn // terminate on exit
b .
exception:
mfsprg2 %r0
cmpdi %r0,0
bne call_ret
attn
#define EXCEPTION(nr) \
.= nr ;\
li %r3,nr ;\
b exception
EXCEPTION(0x300)
EXCEPTION(0x380)
EXCEPTION(0x400)
EXCEPTION(0x480)
EXCEPTION(0x500)
EXCEPTION(0x600)
EXCEPTION(0x700)
EXCEPTION(0x800)
EXCEPTION(0x900)
EXCEPTION(0x980)
EXCEPTION(0xa00)
EXCEPTION(0xb00)
EXCEPTION(0xd00)
EXCEPTION(0xe00)
EXCEPTION(0xe20)
EXCEPTION(0xe40)
EXCEPTION(0xe60)
EXCEPTION(0xe80)
EXCEPTION(0xf00)
EXCEPTION(0xf20)
EXCEPTION(0xf40)
EXCEPTION(0xf60)
EXCEPTION(0xf80)
. = 0x1000
/*
* This page gets mapped at various locations and
* the tests try to execute from it.
* r3 contains the test number.
*/
.globl test_code
test_code:
nop
nop
mflr %r9
cmpdi %r3,1
beq test_1
cmpdi %r3,2
beq test_2
cmpdi %r3,3
beq test_3
li %r3,0
blr
/* test a doubleword load from memory */
test_1: ld %r3,0(%r4)
blr
/* test a branch from the page at fffff000 */
test_2:
b test_2a + 0x1000
test_2a:
b test_2b - 0x1000
test_2b:
beq test_2c + 0x1000
test_2c:
beq test_2d - 0x1000
test_2d:
li %r3,0
blr
test_return:
mflr %r3
mtlr %r9
blr
. = 0x1ffc
/* test a branch with link from the 4G-4 address */
test_3: bl test_return
.globl test_code_end
test_code_end:
. = 0x2000
/*
* Call a function in a context with a given MSR value.
* r3, r4 = args; r5 = function; r6 = MSR
*/
.globl callit
callit:
mflr %r0
std %r0,16(%r1)
stdu %r1,-256(%r1)
mfcr %r8
stw %r8,100(%r1)
std %r13,104(%r1)
std %r14,112(%r1)
std %r15,120(%r1)
std %r16,128(%r1)
std %r17,136(%r1)
std %r18,144(%r1)
std %r19,152(%r1)
std %r20,160(%r1)
std %r21,168(%r1)
std %r22,176(%r1)
std %r23,184(%r1)
std %r24,192(%r1)
std %r25,200(%r1)
std %r26,208(%r1)
std %r27,216(%r1)
std %r28,224(%r1)
std %r29,232(%r1)
std %r30,240(%r1)
std %r31,248(%r1)
li %r0,restore@l
mtsprg0 %r0
mtsprg1 %r1
mtsprg2 %r2
mfmsr %r9
mtsprg3 %r9
li %r10,call_ret@l
mtlr %r10
mtsrr0 %r5
mtsrr1 %r6
mr %r12,%r5
rfid
call_ret:
tdi 0,%r0,0x48 /* b .+8 if wrong endian */
b 2f /* if endian OK */
/* reverse-endian version of instructions from 2: on */
.long 0xa642107c
.long 0xa642937c
.long 0xa602ba7c
.long 0xa602db7c
.long 0xa643b07c
.long 0xa643d37c
.long 0xa6031a7c
.long 0xa6039b7c
.long 0x2400004c
2: mfsprg0 %r0
mfsprg3 %r4
mfsrr0 %r5
mfsrr1 %r6
mtsprg0 %r5
mtsprg3 %r6
mtsrr0 %r0
mtsrr1 %r4
rfid
restore:
mfsprg1 %r1
mfsprg2 %r2
li %r7,0
mtsprg2 %r7
lwz %r8,100(%r1)
mtcr %r8
ld %r13,104(%r1)
ld %r14,112(%r1)
ld %r15,120(%r1)
ld %r16,128(%r1)
ld %r17,136(%r1)
ld %r18,144(%r1)
ld %r19,152(%r1)
ld %r20,160(%r1)
ld %r21,168(%r1)
ld %r22,176(%r1)
ld %r23,184(%r1)
ld %r24,192(%r1)
ld %r25,200(%r1)
ld %r26,208(%r1)
ld %r27,216(%r1)
ld %r28,224(%r1)
ld %r29,232(%r1)
ld %r30,240(%r1)
ld %r31,248(%r1)
addi %r1,%r1,256
ld %r0,16(%r1)
mtlr %r0
blr

339
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#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "console.h"
#define MSR_LE 0x1
#define MSR_DR 0x10
#define MSR_IR 0x20
#define MSR_SF 0x8000000000000000ul
extern unsigned long callit(unsigned long arg1, unsigned long arg2,
unsigned long fn, unsigned long msr);
static inline void do_tlbie(unsigned long rb, unsigned long rs)
{
__asm__ volatile("tlbie %0,%1" : : "r" (rb), "r" (rs) : "memory");
}
#define DSISR 18
#define DAR 19
#define SRR0 26
#define SRR1 27
#define PID 48
#define SPRG0 272
#define SPRG1 273
#define PRTBL 720
static inline unsigned long mfspr(int sprnum)
{
long val;
__asm__ volatile("mfspr %0,%1" : "=r" (val) : "i" (sprnum));
return val;
}
static inline void mtspr(int sprnum, unsigned long val)
{
__asm__ volatile("mtspr %0,%1" : : "i" (sprnum), "r" (val));
}
static inline void store_pte(unsigned long *p, unsigned long pte)
{
__asm__ volatile("stdbrx %1,0,%0" : : "r" (p), "r" (pte) : "memory");
}
void print_string(const char *str)
{
for (; *str; ++str)
putchar(*str);
}
void print_hex(unsigned long val, int ndigit)
{
int i, x;
for (i = (ndigit - 1) * 4; i >= 0; i -= 4) {
x = (val >> i) & 0xf;
if (x >= 10)
putchar(x + 'a' - 10);
else
putchar(x + '0');
}
}
// i < 100
void print_test_number(int i)
{
print_string("test ");
putchar(48 + i/10);
putchar(48 + i%10);
putchar(':');
}
#define CACHE_LINE_SIZE 64
void zero_memory(void *ptr, unsigned long nbytes)
{
unsigned long nb, i, nl;
void *p;
for (; nbytes != 0; nbytes -= nb, ptr += nb) {
nb = -((unsigned long)ptr) & (CACHE_LINE_SIZE - 1);
if (nb == 0 && nbytes >= CACHE_LINE_SIZE) {
nl = nbytes / CACHE_LINE_SIZE;
p = ptr;
for (i = 0; i < nl; ++i) {
__asm__ volatile("dcbz 0,%0" : : "r" (p) : "memory");
p += CACHE_LINE_SIZE;
}
nb = nl * CACHE_LINE_SIZE;
} else {
if (nb > nbytes)
nb = nbytes;
for (i = 0; i < nb; ++i)
((unsigned char *)ptr)[i] = 0;
}
}
}
#define PERM_EX 0x001
#define PERM_WR 0x002
#define PERM_RD 0x004
#define PERM_PRIV 0x008
#define ATTR_NC 0x020
#define CHG 0x080
#define REF 0x100
#define DFLT_PERM (PERM_EX | PERM_WR | PERM_RD | REF | CHG)
/*
* Set up an MMU translation tree using memory starting at the 64k point.
* We use 3 levels, mapping 512GB, with 4kB PGD/PMD/PTE pages.
*/
unsigned long *proc_tbl = (unsigned long *) 0x10000;
unsigned long *pgdir = (unsigned long *) 0x11000;
unsigned long free_ptr = 0x12000;
void init_mmu(void)
{
/* set up process table */
zero_memory(proc_tbl, 512 * sizeof(unsigned long));
mtspr(PRTBL, (unsigned long)proc_tbl);
mtspr(PID, 1);
zero_memory(pgdir, 512 * sizeof(unsigned long));
/* RTS = 8 (512GB address space), RPDS = 9 (512-entry top level) */
store_pte(&proc_tbl[2 * 1], (unsigned long) pgdir | 0x2000000000000009);
do_tlbie(0xc00, 0); /* invalidate all TLB entries */
}
static unsigned long *read_pd(unsigned long *pdp, unsigned long i)
{
unsigned long ret;
__asm__ volatile("ldbrx %0,%1,%2" : "=r" (ret) : "b" (pdp),
"r" (i * sizeof(unsigned long)));
return (unsigned long *) (ret & 0x00ffffffffffff00);
}
void map(unsigned long ea, unsigned long pa, unsigned long perm_attr)
{
unsigned long epn = ea >> 12;
unsigned long h, i, j;
unsigned long *ptep;
unsigned long *pmdp;
h = (epn >> 18) & 0x1ff;
i = (epn >> 9) & 0x1ff;
j = epn & 0x1ff;
if (pgdir[h] == 0) {
zero_memory((void *)free_ptr, 512 * sizeof(unsigned long));
store_pte(&pgdir[h], 0x8000000000000000 | free_ptr | 9);
free_ptr += 512 * sizeof(unsigned long);
}
pmdp = read_pd(pgdir, h);
if (pmdp[i] == 0) {
zero_memory((void *)free_ptr, 512 * sizeof(unsigned long));
store_pte(&pmdp[i], 0x8000000000000000 | free_ptr | 9);
free_ptr += 512 * sizeof(unsigned long);
}
ptep = read_pd(pmdp, i);
if (ptep[j]) {
ptep[j] = 0;
do_tlbie(ea & ~0xfff, 0);
}
store_pte(&ptep[j], 0xc000000000000000 | (pa & 0x00fffffffffff000) |
perm_attr);
}
void unmap(void *ea)
{
unsigned long epn = (unsigned long) ea >> 12;
unsigned long h, i, j;
unsigned long *ptep, *pmdp;
h = (epn >> 18) & 0x1ff;
i = (epn >> 9) & 0x1ff;
j = epn & 0x1ff;
if (pgdir[h] == 0)
return;
pmdp = read_pd(pgdir, h);
if (pmdp[i] == 0)
return;
ptep = read_pd(pmdp, i);
ptep[j] = 0;
do_tlbie(((unsigned long)ea & ~0xfff), 0);
}
extern unsigned long test_code(unsigned long sel, unsigned long addr);
static unsigned long bits = 0x0102030405060708ul;
int mode_test_1(void)
{
unsigned long ret, msr;
msr = MSR_SF | MSR_IR | MSR_DR | MSR_LE;
ret = callit(1, (unsigned long)&bits, (unsigned long)&test_code, msr);
if (ret != bits)
return ret? ret: 1;
return 0;
}
unsigned long be_test_code;
int mode_test_2(void)
{
unsigned long i;
unsigned int *src, *dst;
unsigned long ret, msr;
/* copy and byte-swap the page containing test_code */
be_test_code = free_ptr;
free_ptr += 0x1000;
src = (unsigned int *) &test_code;
dst = (unsigned int *) be_test_code;
for (i = 0; i < 0x1000 / sizeof(unsigned int); ++i)
dst[i] = __builtin_bswap32(src[i]);
__asm__ volatile("isync; icbi 0,%0" : : "r" (be_test_code));
map(be_test_code, be_test_code, DFLT_PERM);
msr = MSR_SF | MSR_IR | MSR_DR;
ret = callit(1, (unsigned long)&bits, be_test_code, msr);
if (ret != __builtin_bswap64(bits))
return ret? ret: 1;
return 0;
}
int mode_test_3(void)
{
unsigned long ret, msr;
unsigned long addr = (unsigned long) &bits;
unsigned long code = (unsigned long) &test_code;
msr = MSR_IR | MSR_DR | MSR_LE;
ret = callit(1, addr, code, msr);
if (ret != bits)
return ret? ret: 1;
ret = callit(1, addr + 0x5555555500000000ul,
code + 0x9999999900000000ul, msr);
if (ret != bits)
return ret? ret: 2;
return 0;
}
int mode_test_4(void)
{
unsigned long ret, msr;
unsigned long addr = (unsigned long) &bits;
msr = MSR_IR | MSR_DR;
ret = callit(1, addr, be_test_code, msr);
if (ret != __builtin_bswap64(bits))
return ret? ret: 1;
ret = callit(1, addr + 0x5555555500000000ul,
be_test_code + 0x9999999900000000ul, msr);
if (ret != __builtin_bswap64(bits))
return ret? ret: 2;
return 0;
}
int mode_test_5(void)
{
unsigned long ret, msr;
/*
* Try branching from the page at fffff000
* to the page at 0 in 32-bit mode.
*/
map(0xfffff000, (unsigned long) &test_code, DFLT_PERM);
map(0, (unsigned long) &test_code, DFLT_PERM);
msr = MSR_IR | MSR_DR | MSR_LE;
ret = callit(2, 0, 0xfffff000, msr);
return ret;
}
int mode_test_6(void)
{
unsigned long ret, msr;
/*
* Try a bl from address fffffffc in 32-bit mode.
* We expect LR to be set to 100000000, though the
* arch says the value is undefined.
*/
msr = MSR_IR | MSR_DR | MSR_LE;
ret = callit(3, 0, 0xfffff000, msr);
if (ret != 0x100000000ul)
return 1;
return 0;
}
int fail = 0;
void do_test(int num, int (*test)(void))
{
int ret;
print_test_number(num);
ret = test();
if (ret == 0) {
print_string("PASS\r\n");
} else {
fail = 1;
print_string("FAIL ");
print_hex(ret, 16);
if (ret != 0 && (ret & ~0xfe0ul) == 0) {
print_string(" SRR0=");
print_hex(mfspr(SPRG0), 16);
print_string(" SRR1=");
print_hex(mfspr(SPRG1), 16);
}
print_string("\r\n");
}
}
int main(void)
{
unsigned long addr;
extern unsigned char __stack_top[];
console_init();
init_mmu();
/*
* Map test code and stack 1-1
*/
for (addr = 0; addr < (unsigned long)&__stack_top; addr += 0x1000)
map(addr, addr, DFLT_PERM);
do_test(1, mode_test_1);
do_test(2, mode_test_2);
do_test(3, mode_test_3);
do_test(4, mode_test_4);
do_test(5, mode_test_5);
do_test(6, mode_test_6);
return fail;
}

27
tests/modes/powerpc.lds Normal file
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SECTIONS
{
. = 0;
_start = .;
.head : {
KEEP(*(.head))
}
. = ALIGN(0x1000);
.text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
. = ALIGN(0x1000);
.data : { *(.data) *(.data.*) *(.got) *(.toc) }
. = ALIGN(0x80);
__bss_start = .;
.bss : {
*(.dynsbss)
*(.sbss)
*(.scommon)
*(.dynbss)
*(.bss)
*(.common)
*(.bss.*)
}
. = ALIGN(0x80);
__bss_end = .;
. = . + 0x4000;
__stack_top = .;
}

3
tests/reservation/Makefile Normal file
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TEST=reservation
include ../Makefile.test

157
tests/reservation/head.S Normal file
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/* Copyright 2013-2014 IBM Corp.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
* implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Load an immediate 64-bit value into a register */
#define LOAD_IMM64(r, e) \
lis r,(e)@highest; \
ori r,r,(e)@higher; \
rldicr r,r, 32, 31; \
oris r,r, (e)@h; \
ori r,r, (e)@l;
.section ".head","ax"
/*
* Microwatt currently enters in LE mode at 0x0, so we don't need to
* do any endian fix ups
*/
. = 0
.global _start
_start:
LOAD_IMM64(%r10,__bss_start)
LOAD_IMM64(%r11,__bss_end)
subf %r11,%r10,%r11
addi %r11,%r11,63
srdi. %r11,%r11,6
beq 2f
mtctr %r11
1: dcbz 0,%r10
addi %r10,%r10,64
bdnz 1b
2: LOAD_IMM64(%r1,__stack_top)
li %r0,0
stdu %r0,-16(%r1)
mtsprg2 %r0
LOAD_IMM64(%r12, main)
mtctr %r12
bctrl
attn // terminate on exit
b .
exception:
mfsprg2 %r0
cmpdi %r0,0
bne call_ret
attn
#define EXCEPTION(nr) \
.= nr ;\
li %r3,nr ;\
b exception
EXCEPTION(0x300)
EXCEPTION(0x380)
EXCEPTION(0x400)
EXCEPTION(0x480)
EXCEPTION(0x500)
EXCEPTION(0x600)
EXCEPTION(0x700)
EXCEPTION(0x800)
EXCEPTION(0x900)
EXCEPTION(0x980)
EXCEPTION(0xa00)
EXCEPTION(0xb00)
EXCEPTION(0xc00)
EXCEPTION(0xd00)
EXCEPTION(0xe00)
EXCEPTION(0xe20)
EXCEPTION(0xe40)
EXCEPTION(0xe60)
EXCEPTION(0xe80)
EXCEPTION(0xf00)
EXCEPTION(0xf20)
EXCEPTION(0xf40)
EXCEPTION(0xf60)
EXCEPTION(0xf80)
. = 0x1000
/*
* Call a function in a context with a given MSR value.
* r3, r4 = args; r5 = function
*/
.globl callit
callit:
mflr %r0
std %r0,16(%r1)
stdu %r1,-256(%r1)
mfcr %r8
stw %r8,100(%r1)
std %r13,104(%r1)
std %r14,112(%r1)
std %r15,120(%r1)
std %r16,128(%r1)
std %r17,136(%r1)
std %r18,144(%r1)
std %r19,152(%r1)
std %r20,160(%r1)
std %r21,168(%r1)
std %r22,176(%r1)
std %r23,184(%r1)
std %r24,192(%r1)
std %r25,200(%r1)
std %r26,208(%r1)
std %r27,216(%r1)
std %r28,224(%r1)
std %r29,232(%r1)
std %r30,240(%r1)
std %r31,248(%r1)
mtsprg0 %r0
mtsprg1 %r1
mtsprg2 %r2
mtctr %r5
mr %r12,%r5
bctrl
call_ret:
mfsprg0 %r0 /* restore regs in case of trap */
mfsprg1 %r1
mfsprg2 %r2
li %r7,0
mtsprg2 %r7
mtlr %r0
lwz %r8,100(%r1)
mtcr %r8
ld %r13,104(%r1)
ld %r14,112(%r1)
ld %r15,120(%r1)
ld %r16,128(%r1)
ld %r17,136(%r1)
ld %r18,144(%r1)
ld %r19,152(%r1)
ld %r20,160(%r1)
ld %r21,168(%r1)
ld %r22,176(%r1)
ld %r23,184(%r1)
ld %r24,192(%r1)
ld %r25,200(%r1)
ld %r26,208(%r1)
ld %r27,216(%r1)
ld %r28,224(%r1)
ld %r29,232(%r1)
ld %r30,240(%r1)
ld %r31,248(%r1)
addi %r1,%r1,256
blr

27
tests/reservation/powerpc.lds Normal file
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@ -0,0 +1,27 @@
SECTIONS
{
. = 0;
_start = .;
.head : {
KEEP(*(.head))
}
. = ALIGN(0x1000);
.text : { *(.text) *(.text.*) *(.rodata) *(.rodata.*) }
. = ALIGN(0x1000);
.data : { *(.data) *(.data.*) *(.got) *(.toc) }
. = ALIGN(0x80);
__bss_start = .;
.bss : {
*(.dynsbss)
*(.sbss)
*(.scommon)
*(.dynbss)
*(.bss)
*(.common)
*(.bss.*)
}
. = ALIGN(0x80);
__bss_end = .;
. = . + 0x4000;
__stack_top = .;
}

210
tests/reservation/reservation.c Normal file
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#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "console.h"
extern unsigned long callit(unsigned long arg1, unsigned long arg2,
unsigned long (*fn)(unsigned long, unsigned long));
#define DSISR 18
#define DAR 19
#define SRR0 26
#define SRR1 27
#define PID 48
#define SPRG0 272
#define SPRG1 273
#define PRTBL 720
static inline unsigned long mfspr(int sprnum)
{
long val;
__asm__ volatile("mfspr %0,%1" : "=r" (val) : "i" (sprnum));
return val;
}
static inline void mtspr(int sprnum, unsigned long val)
{
__asm__ volatile("mtspr %0,%1" : : "i" (sprnum), "r" (val));
}
static inline void store_pte(unsigned long *p, unsigned long pte)
{
__asm__ volatile("stdbrx %1,0,%0" : : "r" (p), "r" (pte) : "memory");
}
void print_string(const char *str)
{
for (; *str; ++str)
putchar(*str);
}
void print_hex(unsigned long val, int ndigits)
{
int i, x;
for (i = (ndigits - 1) * 4; i >= 0; i -= 4) {
x = (val >> i) & 0xf;
if (x >= 10)
putchar(x + 'a' - 10);
else
putchar(x + '0');
}
}
// i < 100
void print_test_number(int i)
{
print_string("test ");
putchar(48 + i/10);
putchar(48 + i%10);
putchar(':');
}
#define DO_LARX(instr, addr, val) __asm__ volatile(instr " %0,0,%1" : "=r" (val) : "r" (addr))
#define DO_STCX(instr, addr, val, cc) __asm__ volatile(instr " %2,0,%1; mfcr %0" : "=r" (cc) \
: "r" (addr), "r" (val) : "cr0", "memory");
int resv_test_1(void)
{
unsigned long x, val, cc = 0;
int count;
x = 1234;
for (count = 0; count < 1000; ++count) {
DO_LARX("ldarx", &x, val);
DO_STCX("stdcx.", &x, 5678, cc);
if (cc & 0x20000000)
break;
}
/* ldarx/stdcx. should succeed eventually */
if (count == 1000)
return 1;
if (x != 5678)
return 2;
for (count = 0; count < 1000; ++count) {
DO_LARX("lwarx", &x, val);
DO_STCX("stwcx.", &x, 9876, cc);
if (cc & 0x20000000)
break;
}
/* lwarx/stwcx. should succeed eventually */
if (count == 1000)
return 3;
if (x != 9876)
return 4;
for (count = 0; count < 1000; ++count) {
DO_LARX("lharx", &x, val);
DO_STCX("sthcx.", &x, 3210, cc);
if (cc & 0x20000000)
break;
}
/* lharx/sthcx. should succeed eventually */
if (count == 1000)
return 5;
if (x != 3210)
return 6;
return 0;
}
unsigned long do_larx(unsigned long size, unsigned long addr)
{
unsigned long val;
switch (size) {
case 1:
DO_LARX("lbarx", addr, val);
break;
case 2:
DO_LARX("lharx", addr, val);
break;
case 4:
DO_LARX("lwarx", addr, val);
break;
case 8:
DO_LARX("ldarx", addr, val);
break;
}
return 0;
}
unsigned long do_stcx(unsigned long size, unsigned long addr)
{
unsigned long val = 0, cc;
switch (size) {
case 1:
DO_STCX("stbcx.", addr, val, cc);
break;
case 2:
DO_STCX("sthcx.", addr, val, cc);
break;
case 4:
DO_STCX("stwcx.", addr, val, cc);
break;
case 8:
DO_STCX("stdcx.", addr, val, cc);
break;
}
return 0;
}
int resv_test_2(void)
{
unsigned long x[3];
unsigned long offset, j, size, ret;
x[0] = 1234;
x[1] = x[2] = 0;
for (j = 0; j <= 3; ++j) {
size = 1 << j;
for (offset = 0; offset < 16; ++offset) {
ret = callit(size, (unsigned long)&x[0] + offset, do_larx);
if (0 && ret == 0 && (offset & (size - 1)) != 0)
return j + 1;
if (ret == 0x600) {
if ((offset & (size - 1)) == 0)
return j + 0x10;
} else if (ret)
return ret;
ret = callit(size, (unsigned long)&x[0] + offset, do_stcx);
if (ret == 0 && (offset & (size - 1)) != 0)
return j + 0x20;
if (ret == 0x600) {
if ((offset & (size - 1)) == 0)
return j + 0x30;
} else if (ret)
return ret;
}
}
return 0;
}
int fail = 0;
void do_test(int num, int (*test)(void))
{
int ret;
print_test_number(num);
ret = test();
if (ret == 0) {
print_string("PASS\r\n");
} else {
fail = 1;
print_string("FAIL ");
print_hex(ret, 4);
print_string("\r\n");
}
}
int main(void)
{
console_init();
do_test(1, resv_test_1);
do_test(2, resv_test_2);
return fail;
}

BIN
tests/test_mmu.bin
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BIN
tests/test_modes.bin Executable file
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6
tests/test_modes.console_out Normal file
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@ -0,0 +1,6 @@
test 01:PASS
test 02:PASS
test 03:PASS
test 04:PASS
test 05:PASS
test 06:PASS

BIN
tests/test_reservation.bin Executable file
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2
tests/test_reservation.console_out Normal file
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@ -0,0 +1,2 @@
test 01:PASS
test 02:PASS

2
tests/update_console_tests
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@ -3,7 +3,7 @@
# Script to update console related tests from source
#
for i in sc illegal decrementer xics privileged mmu misc ; do
for i in sc illegal decrementer xics privileged mmu misc modes reservation ; do
cd $i
make
cd -

9
writeback.vhdl
View File

@ -99,8 +99,13 @@ begin
-- Perform CR0 update for RC forms
-- Note that loads never have a form with an RC bit, therefore this can test e_in.write_data
if e_in.rc = '1' and e_in.write_enable = '1' then
sign := e_in.write_data(63);
zero := not (or e_in.write_data);
zero := not (or e_in.write_data(31 downto 0));
if e_in.mode_32bit = '0' then
sign := e_in.write_data(63);
zero := zero and not (or e_in.write_data(63 downto 32));
else
sign := e_in.write_data(31);
end if;
c_out.write_cr_enable <= '1';
c_out.write_cr_mask <= num_to_fxm(0);
cf(3) := sign;