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FPU: Make FPSCR bit 11 always read as 0

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Bit 11 (52 in BE numbering) is a reserved bit.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
This commit is contained in:
Paul Mackerras
2025-12-06 18:23:27 +11:00
parent ca792f3b13
commit de71a6119c
3 changed files with 3 additions and 2 deletions
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tests/fpu/fpu.c
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@@ -274,6 +274,7 @@ void set_fpscr(unsigned long fpscr)
unsigned long fpscr_eval(unsigned long val)
{
val &= ~0x60000000; /* clear FEX and VX */
val &= ~0x00000800; /* clear reserved bit 52 (BE) */
if (val & 0x1f80700) /* test all VX* bits */
val |= 0x20000000;
if ((val >> 25) & (val >> 3) & 0x1f)