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Reformat wishbone code

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Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
This commit is contained in:
Anton Blanchard 2019-09-19 20:35:42 +10:00 committed by Anton Blanchard
parent 06392e7eaa
commit df1165bdfc
2 changed files with 58 additions and 58 deletions
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80
wishbone_arbiter.vhdl
View File

@ -5,53 +5,53 @@ library work;
use work.wishbone_types.all;
entity wishbone_arbiter is
port (
clk : in std_ulogic;
rst : in std_ulogic;
port (
clk : in std_ulogic;
rst : in std_ulogic;
wb1_in : in wishbone_master_out;
wb1_out : out wishbone_slave_out;
wb1_in : in wishbone_master_out;
wb1_out : out wishbone_slave_out;
wb2_in : in wishbone_master_out;
wb2_out : out wishbone_slave_out;
wb2_in : in wishbone_master_out;
wb2_out : out wishbone_slave_out;
wb_out : out wishbone_master_out;
wb_in : in wishbone_slave_out
);
wb_out : out wishbone_master_out;
wb_in : in wishbone_slave_out
);
end wishbone_arbiter;
architecture behave of wishbone_arbiter is
type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY);
signal state : wishbone_arbiter_state_t := IDLE;
type wishbone_arbiter_state_t is (IDLE, WB1_BUSY, WB2_BUSY);
signal state : wishbone_arbiter_state_t := IDLE;
begin
wb1_out <= wb_in when state = WB1_BUSY else wishbone_slave_out_init;
wb2_out <= wb_in when state = WB2_BUSY else wishbone_slave_out_init;
wb1_out <= wb_in when state = WB1_BUSY else wishbone_slave_out_init;
wb2_out <= wb_in when state = WB2_BUSY else wishbone_slave_out_init;
wb_out <= wb1_in when state = WB1_BUSY else wb2_in when state = WB2_BUSY else wishbone_master_out_init;
wb_out <= wb1_in when state = WB1_BUSY else wb2_in when state = WB2_BUSY else wishbone_master_out_init;
wishbone_arbiter_process: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= IDLE;
else
case state is
when IDLE =>
if wb1_in.cyc = '1' then
state <= WB1_BUSY;
elsif wb2_in.cyc = '1' then
state <= WB2_BUSY;
end if;
when WB1_BUSY =>
if wb1_in.cyc = '0' then
state <= IDLE;
end if;
when WB2_BUSY =>
if wb2_in.cyc = '0' then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
wishbone_arbiter_process: process(clk)
begin
if rising_edge(clk) then
if rst = '1' then
state <= IDLE;
else
case state is
when IDLE =>
if wb1_in.cyc = '1' then
state <= WB1_BUSY;
elsif wb2_in.cyc = '1' then
state <= WB2_BUSY;
end if;
when WB1_BUSY =>
if wb1_in.cyc = '0' then
state <= IDLE;
end if;
when WB2_BUSY =>
if wb2_in.cyc = '0' then
state <= IDLE;
end if;
end case;
end if;
end if;
end process;
end behave;

36
wishbone_types.vhdl
View File

@ -2,26 +2,26 @@ library ieee;
use ieee.std_logic_1164.all;
package wishbone_types is
constant wishbone_addr_bits : integer := 64;
constant wishbone_data_bits : integer := 64;
constant wishbone_addr_bits : integer := 64;
constant wishbone_data_bits : integer := 64;
subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
type wishbone_master_out is record
adr : wishbone_addr_type;
dat : wishbone_data_type;
cyc : std_ulogic;
stb : std_ulogic;
sel : std_ulogic_vector(7 downto 0);
we : std_ulogic;
end record;
constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0'));
type wishbone_master_out is record
adr : wishbone_addr_type;
dat : wishbone_data_type;
cyc : std_ulogic;
stb : std_ulogic;
sel : std_ulogic_vector(7 downto 0);
we : std_ulogic;
end record;
constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0'));
type wishbone_slave_out is record
dat : wishbone_data_type;
ack : std_ulogic;
end record;
constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0'));
type wishbone_slave_out is record
dat : wishbone_data_type;
ack : std_ulogic;
end record;
constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0'));
end package wishbone_types;