mirror of
https://github.com/antonblanchard/microwatt.git
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Anton Blanchard
GitHub
commit
f181bf31e2
6
Makefile
6
Makefile
@ -3,7 +3,7 @@ GHDLFLAGS=--std=08 -Psim-unisim
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CFLAGS=-O2 -Wall
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all = core_tb simple_ram_behavioural_tb soc_reset_tb icache_tb multiply_tb dmi_dtm_tb divider_tb \
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rotator_tb
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rotator_tb countzero_tb
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# XXX
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# loadstore_tb fetch_tb
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@ -19,6 +19,7 @@ core_tb.o: common.o wishbone_types.o core.o soc.o sim_jtag.o
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core.o: common.o wishbone_types.o fetch1.o fetch2.o icache.o decode1.o decode2.o register_file.o cr_file.o execute1.o execute2.o loadstore1.o loadstore2.o multiply.o writeback.o core_debug.o divider.o
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core_debug.o: common.o
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countzero.o:
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countzero_tb.o: common.o glibc_random.o countzero.o
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cr_file.o: common.o
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crhelpers.o: common.o
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decode1.o: common.o decode_types.o
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@ -95,6 +96,9 @@ divider_tb: divider_tb.o
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rotator_tb: rotator_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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countzero_tb: countzero_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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simple_ram_tb: simple_ram_tb.o
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$(GHDL) -e $(GHDLFLAGS) $@
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171
countzero.vhdl
171
countzero.vhdl
@ -14,97 +14,100 @@ entity zero_counter is
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end entity zero_counter;
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architecture behaviour of zero_counter is
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signal y, z : std_ulogic_vector(3 downto 0);
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signal v16 : std_ulogic_vector(15 downto 0);
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signal v4 : std_ulogic_vector(3 downto 0);
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signal sel : std_ulogic_vector(5 downto 0);
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-- Return the index of the leftmost or rightmost 1 in a set of 4 bits.
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-- Assumes v is not "0000"; if it is, return (right ? "11" : "00").
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function encoder(v: std_ulogic_vector(3 downto 0); right: std_ulogic) return std_ulogic_vector is
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begin
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if right = '0' then
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if v(3) = '1' then
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return "11";
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elsif v(2) = '1' then
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return "10";
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elsif v(1) = '1' then
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return "01";
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else
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return "00";
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end if;
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else
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if v(0) = '1' then
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return "00";
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elsif v(1) = '1' then
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return "01";
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elsif v(2) = '1' then
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return "10";
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else
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return "11";
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end if;
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end if;
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end;
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begin
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zerocounter0: process(all)
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variable l32, r32 : std_ulogic;
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variable v32 : std_ulogic_vector(31 downto 0);
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variable v16 : std_ulogic_vector(15 downto 0);
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variable v8 : std_ulogic_vector(7 downto 0);
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variable v4 : std_ulogic_vector(3 downto 0);
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variable sel : std_ulogic_vector(5 downto 0);
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begin
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l32 := '0';
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r32 := '0';
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v32 := (others => '0');
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v16 := (others => '0');
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v8 := (others => '0');
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v4 := (others => '0');
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sel := (others => '0');
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-- Test 4 groups of 16 bits each.
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-- The top 2 groups are considered to be zero in 32-bit mode.
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z(0) <= or (rs(15 downto 0));
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z(1) <= or (rs(31 downto 16));
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z(2) <= or (rs(47 downto 32));
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z(3) <= or (rs(63 downto 48));
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if is_32bit = '0' then
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sel(5 downto 4) <= encoder(z, count_right);
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else
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sel(5) <= '0';
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if count_right = '0' then
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sel(4) <= z(1);
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else
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sel(4) <= not z(0);
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end if;
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end if;
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l32 := or (rs(63 downto 32));
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r32 := or (rs(31 downto 0));
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if (l32 = '0' or is_32bit = '1') and r32 = '0' then
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-- Select the leftmost/rightmost non-zero group of 16 bits
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case sel(5 downto 4) is
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when "00" =>
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v16 <= rs(15 downto 0);
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when "01" =>
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v16 <= rs(31 downto 16);
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when "10" =>
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v16 <= rs(47 downto 32);
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when others =>
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v16 <= rs(63 downto 48);
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end case;
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-- Test 4 groups of 4 bits
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y(0) <= or (v16(3 downto 0));
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y(1) <= or (v16(7 downto 4));
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y(2) <= or (v16(11 downto 8));
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y(3) <= or (v16(15 downto 12));
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sel(3 downto 2) <= encoder(y, count_right);
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-- Select the leftmost/rightmost non-zero group of 4 bits
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case sel(3 downto 2) is
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when "00" =>
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v4 <= v16(3 downto 0);
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when "01" =>
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v4 <= v16(7 downto 4);
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when "10" =>
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v4 <= v16(11 downto 8);
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when others =>
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v4 <= v16(15 downto 12);
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end case;
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sel(1 downto 0) <= encoder(v4, count_right);
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-- sel is now the index of the leftmost/rightmost 1 bit in rs
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if v4 = "0000" then
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-- operand is zero, return 32 for 32-bit, else 64
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result <= x"00000000000000" & '0' & not is_32bit & is_32bit & "00000";
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elsif count_right = '0' then
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-- return (63 - sel), trimmed to 5 bits in 32-bit mode
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result <= x"00000000000000" & "00" & (not sel(5) and not is_32bit) & not sel(4 downto 0);
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else
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if count_right = '0' then
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sel(5) := l32 and (not is_32bit);
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else
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sel(5) := (not r32) and (not is_32bit);
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end if;
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if sel(5) = '1' then
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v32 := rs(63 downto 32);
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else
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v32 := rs(31 downto 0);
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end if;
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if count_right = '0' then
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sel(4) := or (v32(31 downto 16));
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else
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sel(4) := not (or (v32(15 downto 0)));
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end if;
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if sel(4) = '1' then
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v16 := v32(31 downto 16);
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else
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v16 := v32(15 downto 0);
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end if;
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if count_right = '0' then
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sel(3) := or (v16(15 downto 8));
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else
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sel(3) := not (or (v16(7 downto 0)));
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end if;
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if sel(3) = '1' then
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v8 := v16(15 downto 8);
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else
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v8 := v16(7 downto 0);
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end if;
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if count_right = '0' then
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sel(2) := or (v8(7 downto 4));
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else
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sel(2) := not (or (v8(3 downto 0)));
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end if;
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if sel(2) = '1' then
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v4 := v8(7 downto 4);
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else
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v4 := v8(3 downto 0);
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end if;
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if count_right = '0' then
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if v4(3) = '1' then
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sel(1 downto 0) := "11";
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elsif v4(2) = '1' then
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sel(1 downto 0) := "10";
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elsif v4(1) = '1' then
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sel(1 downto 0) := "01";
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else
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sel(1 downto 0) := "00";
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end if;
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result <= x"00000000000000" & "00" & (not sel(5) and not is_32bit) & not sel(4 downto 0);
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else
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if v4(0) = '1' then
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sel(1 downto 0) := "00";
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elsif v4(1) = '1' then
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sel(1 downto 0) := "01";
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elsif v4(2) = '1' then
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sel(1 downto 0) := "10";
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else
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sel(1 downto 0) := "11";
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end if;
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result <= x"00000000000000" & "00" & sel;
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end if;
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result <= x"00000000000000" & "00" & sel;
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end if;
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end process;
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105
countzero_tb.vhdl
Normal file
105
countzero_tb.vhdl
Normal file
@ -0,0 +1,105 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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use work.glibc_random.all;
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entity countzero_tb is
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end countzero_tb;
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architecture behave of countzero_tb is
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constant clk_period: time := 10 ns;
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signal rs: std_ulogic_vector(63 downto 0);
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signal is_32bit, count_right: std_ulogic := '0';
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signal result: std_ulogic_vector(63 downto 0);
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signal randno: std_ulogic_vector(63 downto 0);
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begin
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zerocounter_0: entity work.zero_counter
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port map (
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rs => rs,
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result => result,
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count_right => count_right,
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is_32bit => is_32bit
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);
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stim_process: process
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variable r: std_ulogic_vector(63 downto 0);
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begin
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-- test with input = 0
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report "test zero input";
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rs <= (others => '0');
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is_32bit <= '0';
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count_right <= '0';
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wait for clk_period;
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assert result = x"0000000000000040"
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report "bad cntlzd 0 = " & to_hstring(result);
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count_right <= '1';
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wait for clk_period;
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assert result = x"0000000000000040"
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report "bad cnttzd 0 = " & to_hstring(result);
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is_32bit <= '1';
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count_right <= '0';
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wait for clk_period;
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assert result = x"0000000000000020"
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report "bad cntlzw 0 = " & to_hstring(result);
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count_right <= '1';
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wait for clk_period;
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assert result = x"0000000000000020"
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report "bad cnttzw 0 = " & to_hstring(result);
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report "test cntlzd/w";
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count_right <= '0';
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for j in 0 to 100 loop
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r := pseudorand(64);
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r(63) := '1';
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for i in 0 to 63 loop
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rs <= r;
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is_32bit <= '0';
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wait for clk_period;
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assert to_integer(unsigned(result)) = i
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report "bad cntlzd " & to_hstring(rs) & " -> " & to_hstring(result);
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rs <= r(31 downto 0) & r(63 downto 32);
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is_32bit <= '1';
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wait for clk_period;
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if i < 32 then
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assert to_integer(unsigned(result)) = i
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report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
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else
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assert to_integer(unsigned(result)) = 32
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report "bad cntlzw " & to_hstring(rs) & " -> " & to_hstring(result);
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end if;
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r := '0' & r(63 downto 1);
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end loop;
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end loop;
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report "test cnttzd/w";
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count_right <= '1';
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for j in 0 to 100 loop
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r := pseudorand(64);
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r(0) := '1';
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for i in 0 to 63 loop
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rs <= r;
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is_32bit <= '0';
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wait for clk_period;
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assert to_integer(unsigned(result)) = i
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report "bad cnttzd " & to_hstring(rs) & " -> " & to_hstring(result);
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is_32bit <= '1';
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wait for clk_period;
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if i < 32 then
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assert to_integer(unsigned(result)) = i
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report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
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else
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assert to_integer(unsigned(result)) = 32
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report "bad cnttzw " & to_hstring(rs) & " -> " & to_hstring(result);
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end if;
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r := r(62 downto 0) & '0';
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end loop;
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end loop;
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assert false report "end of test" severity failure;
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wait;
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end process;
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end behave;
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