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https://github.com/antonblanchard/microwatt.git
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icache: Reformat icache
No code change Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
48
icache.vhdl
48
icache.vhdl
@@ -140,33 +140,33 @@ begin
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r.w.we <= '0';
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r.w.we <= '0';
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case r.state is
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case r.state is
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when IDLE =>
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when IDLE =>
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if read_miss = true then
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if read_miss = true then
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r.state <= WAIT_ACK;
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r.state <= WAIT_ACK;
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r.store_word <= 0;
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r.store_word <= 0;
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r.store_index <= read_index;
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r.store_index <= read_index;
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tags(read_index) <= read_tag;
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tags(read_index) <= read_tag;
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tags_valid(read_index) <= '0';
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tags_valid(read_index) <= '0';
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r.w.adr <= i_in.addr(63 downto OFFSET_BITS) & (OFFSET_BITS-1 downto 0 => '0');
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r.w.adr <= i_in.addr(63 downto OFFSET_BITS) & (OFFSET_BITS-1 downto 0 => '0');
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r.w.cyc <= '1';
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r.w.cyc <= '1';
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r.w.stb <= '1';
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r.w.stb <= '1';
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end if;
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end if;
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when WAIT_ACK =>
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when WAIT_ACK =>
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if wishbone_in.ack = '1' then
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if wishbone_in.ack = '1' then
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cachelines(r.store_index)((r.store_word+1)*64-1 downto ((r.store_word)*64)) <= wishbone_in.dat;
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cachelines(r.store_index)((r.store_word+1)*64-1 downto ((r.store_word)*64)) <= wishbone_in.dat;
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r.store_word <= r.store_word + 1;
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r.store_word <= r.store_word + 1;
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if r.store_word = (LINE_SIZE_DW-1) then
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if r.store_word = (LINE_SIZE_DW-1) then
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r.state <= IDLE;
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r.state <= IDLE;
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tags_valid(r.store_index) <= '1';
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tags_valid(r.store_index) <= '1';
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r.w.cyc <= '0';
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r.w.cyc <= '0';
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r.w.stb <= '0';
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r.w.stb <= '0';
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else
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else
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r.w.adr(OFFSET_BITS-1 downto 3) <= std_ulogic_vector(to_unsigned(r.store_word+1, OFFSET_BITS-3));
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r.w.adr(OFFSET_BITS-1 downto 3) <= std_ulogic_vector(to_unsigned(r.store_word+1, OFFSET_BITS-3));
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end if;
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end if;
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end if;
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end if;
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end case;
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end case;
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end if;
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end if;
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end process;
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end process;
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