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uart: Make 16550 the default

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Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt 2020-06-18 17:14:55 +10:00
parent b230677e93
commit fb5c16d05e
5 changed files with 5 additions and 5 deletions
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2
fpga/top-arty.vhdl
View File

@ -24,7 +24,7 @@ entity toplevel is
LOG_LENGTH : natural := 512;
USE_LITEETH : boolean := false;
UART_IS_16550 : boolean := false;
HAS_UART1 : boolean := false
HAS_UART1 : boolean := true
);
port(
ext_clk : in std_ulogic;

2
fpga/top-generic.vhdl
View File

@ -12,7 +12,7 @@ entity toplevel is
CLK_INPUT : positive := 100000000;
CLK_FREQUENCY : positive := 100000000;
DISABLE_FLATTEN_CORE : boolean := false;
UART_IS_16550 : boolean := false
UART_IS_16550 : boolean := true
);
port(
ext_clk : in std_ulogic;

2
fpga/top-nexys-video.vhdl
View File

@ -20,7 +20,7 @@ entity toplevel is
SPI_FLASH_OFFSET : integer := 10485760;
SPI_FLASH_DEF_CKDV : natural := 1;
SPI_FLASH_DEF_QUAD : boolean := true;
UART_IS_16550 : boolean := false;
UART_IS_16550 : boolean := true;
);
port(
ext_clk : in std_ulogic;

2
microwatt.core
View File

@ -315,7 +315,7 @@ parameters:
datatype : bool
description : Use 16550-compatible UART from OpenCores
paramtype : generic
default : false
default : true
has_uart1:
datatype : bool

2
soc.vhdl
View File

@ -63,7 +63,7 @@ entity soc is
SPI_FLASH_DEF_QUAD : boolean := false;
LOG_LENGTH : natural := 512;
HAS_LITEETH : boolean := false;
UART0_IS_16550 : boolean := false;
UART0_IS_16550 : boolean := true;
HAS_UART1 : boolean := false
);
port(