github.com/antonblanchard.microwatt
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asic-3
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9 Commits

Author SHA1 Message Date
Anton Blanchard
c7ef75b55c Forgot multiply.vhdl 2022-02-01 20:55:28 +11:00
Anton Blanchard
e70d7f0a60 Make caches 1 way 2022-02-01 20:44:26 +11:00
Anton Blanchard
7da4977028 Disable FPU 2022-02-01 20:44:26 +11:00
Anton Blanchard
1383bbb8be Add GPIOs 2022-02-01 20:44:26 +11:00
Anton Blanchard
46a85cb274 Add asic alternate reset address 2022-02-01 20:44:26 +11:00
Anton Blanchard
4e9001ba19 Hook up JTAG to asic top level 2022-02-01 20:44:26 +11:00
Anton Blanchard
18503732d7 Add ASIC target 2022-02-01 20:37:14 +11:00
Anton Blanchard
5ac715d932 Fix multiplier behavioural 2022-02-01 20:34:09 +11:00
Anton Blanchard
537a0aac1d Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
 2022-02-01 20:12:06 +11:00