The verilator simulation interface uses the remote_bitbang
protocol from openocd. I have a simple implementation for
urjtag too.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
While verilator finds the correct top level module with the current
setup, if we start adding simulation models it can get confused.
Explicitly specify the top level module.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
Add a microwatt-verilator target that simulates the
ghdl -> yosys -> verilog -> verilator path. A good test of
ghdl/yosys synthesis.
Because the everything is run through synthesis, the instruction
image is baked into the build via the RAM_INIT_FILE generic.
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
