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Commit Graph

4 Commits

Author SHA1 Message Date
Olof Kindgren
12327034d6 Add and use plle2 primitive for nexys boards 2019-08-26 13:44:50 +02:00
Olof Kindgren
b9bf19f912 Added synthesis target
The synth target can be used to analyze the core after synthesis
without running P&R. Currently, the only edalize backends that
support synthesis without P&R are vivado and icestorm, and icestorm
needs yosys built with verific support to parse vhdl.

To run synthesis only for a part, run

fusesoc run --target=synth --tool=vivado microwatt --part=<part>

where part is a valid Xilinx part such as xc7a100tcsg324-1
2019-08-23 14:20:20 +02:00
Olof Kindgren
250d09ed2d Add Nexys Video support 2019-08-23 14:09:06 +02:00
Olof Kindgren
5e56b14125 Add FuseSoC core description file with Nexys A7 support 2019-08-23 13:32:05 +02:00