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mirror of https://github.com/antonblanchard/microwatt.git synced 2026-01-11 23:43:15 +00:00

6 Commits

Author SHA1 Message Date
Anton Blanchard
7994b98404 Fix some whitespace issues
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2021-08-09 11:57:00 +10:00
Benjamin Herrenschmidt
dbb137437c acorn: Add support for the Acorn CLE 215+
This is a NiteFury based PCIe M2 form-factor board originally
used for mining. It contains a speed grade 2 Artix 7 200T,
1GB of DDR3 and 32MB of flash.

The serial port is routed to pin 2 (RX) and 3 (TX) of the P2
connector (pin 1 is GND).

Note: Only 16MB of flash is currently usable until code is added
to configure the flash controller to use 4-bytes address commands
on that part.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-08-07 15:42:07 +10:00
Benjamin Herrenschmidt
9961d70dfb Improve PLL/MMCM clocks configuration
We can now pass both the input clock and target clock frequency
via generics. Add support for both 50Mhz and 100Mhz target freqs
for both cases.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-30 13:57:36 +10:00
Anton Blanchard
142a722ce4 Remove names from end record statements
These are optional, and vhdlpp from iverilog barfs on them.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2019-09-12 09:04:02 +10:00
Anton Blanchard
03fd06deaf Rework SOC reset
The old reset code was overly complicated and never worked properly.
Replace it with a simpler sequence that uses a couple of shift registers
to assert resets:

- Wait a number of external clock cycles before removing reset from
  the PLL.

- After the PLL locks and the external reset button isn't pressed,
  wait a number of PLL clock cycles before removing reset from the SOC.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2019-09-08 07:40:19 +10:00
Olof Kindgren
12327034d6 Add and use plle2 primitive for nexys boards 2019-08-26 13:44:50 +02:00