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mirror of https://github.com/antonblanchard/microwatt.git synced 2026-02-03 07:10:31 +00:00
Commit Graph

7 Commits

Author SHA1 Message Date
Benjamin Herrenschmidt
98f0994698 Add core debug module
This module adds some simple core controls:

  reset, stop, start, step

along with icache clear and reading the NIA and core
status bits

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org
2019-09-20 16:45:50 +10:00
Anton Blanchard
89849a6856 Add a simple direct mapped icache
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2019-09-12 15:57:00 +10:00
Benjamin Herrenschmidt
3ac1dbc737 Share soc.vhdl between FPGA and sim
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-10 16:57:47 +01:00
Benjamin Herrenschmidt
c97b080d8c Move wishbone arbiter out of the core
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-10 16:50:49 +01:00
Benjamin Herrenschmidt
8bfd6e5eae Use simulated UART in core test bench
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2019-09-09 22:18:55 +10:00
Anton Blanchard
1fa0b332ca micropython only requires 512kB of BRAM
Mikey points out that our stack grows down from 512kB and our
heap is below that too, so we can reduce our BRAM requirements,
which allowing some smaller FPGA boards to work. Not sure why
I thought we were using memory between 512kB and 1MB.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2019-08-27 12:02:00 +10:00
Anton Blanchard
5a29cb4699 Initial import of microwatt
Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2019-08-22 16:46:13 +10:00