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2 Commits

Author SHA1 Message Date
Michael Neuling
83d773090e Fix verific script with new VHDL files 
This really needs to be auto generated, but here we are.

Signed-off-by: Michael Neuling <mikey@neuling.org>
 2019-09-06 15:05:03 +10:00
Michael Neuling
4d5abfb430 Remove dynamic ranges from code 
Some VHDL compilers like verific [1] don't like these, so let's remove
them. Lots of random code changes, but passes make check.

Also add basic script to run verific and generate verilog.

1. https://www.verific.com/

Signed-off-by: Michael Neuling <mikey@neuling.org>
 2019-08-30 16:13:48 +10:00