4 Commits

Author	SHA1	Message	Date
Benjamin Herrenschmidt	c22734d0d9	wb_debug: Add wishbone pipelining support ... Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2019-10-30 13:18:58 +11:00
Benjamin Herrenschmidt	1a63c39704	Make it possible to change wishbone address size ... All that needs to be changed now is the size in wishbone_types.vhdl and the address decoder in soc.vhdl Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2019-10-23 12:37:16 +11:00
Paul Mackerras	a27ed0ec27	wishbone_debug_master: Improve timing ... The current code has the possibility that we could set reg_addr or reg_ctrl and then increment reg_addr in the same cycle, resulting in some long timing paths. Rearrange the code to make it clear that we are not trying to add an auto-increment to data from outside the module; in any given cycle we either set one of reg_addr and reg_ctrl, or we possibly increment reg_addr. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>	2019-10-15 18:16:07 +11:00
Benjamin Herrenschmidt	b46f81fae4	Wishbone debug module ... This adds a debug module off the DMI (debug) bus which can act as a wishbone master to generate read and write cycles. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>	2019-09-20 15:07:49 +10:00