github.com/antonblanchard.microwatt
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3 Commits

Author SHA1 Message Date
Michael Neuling
e5a30a1358 Wire up sim uart TX interrupt 
TX is always ready, so just always sent interrupt when enabled.

No RX interrupt.

Signed-off-by: Michael Neuling <mikey@neuling.org>
 2020-04-23 15:08:09 +10:00
Benjamin Herrenschmidt
3ac1dbc737 Share soc.vhdl between FPGA and sim 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-10 16:57:47 +01:00
Benjamin Herrenschmidt
48b689b665 Add simulated UART design 
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
 2019-09-09 22:18:48 +10:00