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478b787c10
The VUnit log package is a SW style logging framework in VHDL and the check package is an assertion library doing its error reporting with VUnit logging. These testbenches don't use, and do not need, very advanced logging/checking features but the following was possible to improve - Checking equality in VHDL can be quite tedious with a lot of type conversions and long message strings to explain the data received and what was expected. VUnit's check_equal procedure allow comparison between same or similar types and automatically create the error message for you. - The code has report statements used for testbench progress reporting and debugging. These were replaced with the info and debug procedures. info logs are visible by default while debug is not. This means that debug logs don't have to be commented, which they are now, when not used. Instead there is a show procedure making debug messages visible. The show procedure has been commented to hide the debug messages but a more elegant solution is to control visibility from a generic and then set that generic from the command line. I've left this as a TODO but the run script allow you to extend the standard CLI of VUnit to add new options and you can also set generics from the run script. - VUnit log messages are color coded if color codes are supported by the terminal. It makes it quicker to spot messages of different types when there are many log messages. Error messages will always be made visible on the terminal but you must use the -v (verbose) to see other logs. - Some tests have a lot of "metvalue detected" warning messages from the numeric_std package and these clutter the logs when using the -v option. VUnit has a simulator independent option allowing you to suppress those messages. That option has been enabled. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
277 lines
9.1 KiB
VHDL
277 lines
9.1 KiB
VHDL
library vunit_lib;
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context vunit_lib.vunit_context;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.ppc_fx_insns.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity multiply_tb is
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generic (runner_cfg : string := runner_cfg_default);
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end multiply_tb;
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architecture behave of multiply_tb is
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signal clk : std_ulogic;
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constant clk_period : time := 10 ns;
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constant pipeline_depth : integer := 4;
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signal m1 : MultiplyInputType := MultiplyInputInit;
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signal m2 : MultiplyOutputType;
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function absval(x: std_ulogic_vector) return std_ulogic_vector is
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begin
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if x(x'left) = '1' then
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return std_ulogic_vector(- signed(x));
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else
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return x;
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end if;
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end;
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begin
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multiply_0: entity work.multiply
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generic map (PIPELINE_DEPTH => pipeline_depth)
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port map (clk => clk, m_in => m1, m_out => m2);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
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variable si: std_ulogic_vector(15 downto 0);
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variable sign: std_ulogic;
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variable rnd : RandomPType;
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begin
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rnd.InitSeed(stim_process'path_name);
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test_runner_setup(runner, runner_cfg);
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while test_suite loop
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if run("Test interface") then
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wait for clk_period;
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m1.valid <= '1';
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m1.data1 <= x"0000000000001000";
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m1.data2 <= x"0000000000001111";
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wait for clk_period;
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check_false(?? m2.valid, result("for valid"));
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m1.valid <= '0';
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wait for clk_period;
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check_false(?? m2.valid, result("for valid"));
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wait for clk_period;
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check_false(?? m2.valid, result("for valid"));
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wait for clk_period;
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result, 16#1111000#);
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wait for clk_period;
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check_false(?? m2.valid, result("for valid"));
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m1.valid <= '1';
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wait for clk_period;
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check_false(?? m2.valid, result("for valid"));
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result, 16#1111000#);
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elsif run("Test mulld") then
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mulld_loop : for i in 0 to 1000 loop
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ra := rnd.RandSlv(ra'length);
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rb := rnd.RandSlv(rb'length);
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behave_rt := ppc_mulld(ra, rb);
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m1.data1 <= absval(ra);
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m1.data2 <= absval(rb);
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sign := ra(63) xor rb(63);
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m1.not_result <= sign;
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m1.addend <= (others => sign);
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m1.valid <= '1';
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result(63 downto 0), behave_rt, result("for mulld " & to_hstring(behave_rt)));
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end loop;
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elsif run("Test mulhdu") then
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mulhdu_loop : for i in 0 to 1000 loop
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ra := rnd.RandSlv(ra'length);
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rb := rnd.RandSlv(rb'length);
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behave_rt := ppc_mulhdu(ra, rb);
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m1.data1 <= ra;
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m1.data2 <= rb;
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m1.not_result <= '0';
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m1.addend <= (others => '0');
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m1.valid <= '1';
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result(127 downto 64), behave_rt, result("for mulhdu " & to_hstring(behave_rt)));
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end loop;
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elsif run("Test mulhd") then
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mulhd_loop : for i in 0 to 1000 loop
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ra := rnd.RandSlv(ra'length);
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rb := rnd.RandSlv(rb'length);
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behave_rt := ppc_mulhd(ra, rb);
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m1.data1 <= absval(ra);
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m1.data2 <= absval(rb);
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sign := ra(63) xor rb(63);
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m1.not_result <= sign;
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m1.addend <= (others => sign);
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m1.valid <= '1';
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result(127 downto 64), behave_rt, result("for mulhd " & to_hstring(behave_rt)));
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end loop;
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elsif run("Test mullw") then
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mullw_loop : for i in 0 to 1000 loop
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ra := rnd.RandSlv(ra'length);
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rb := rnd.RandSlv(rb'length);
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behave_rt := ppc_mullw(ra, rb);
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m1.data1 <= (others => '0');
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m1.data1(31 downto 0) <= absval(ra(31 downto 0));
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m1.data2 <= (others => '0');
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m1.data2(31 downto 0) <= absval(rb(31 downto 0));
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sign := ra(31) xor rb(31);
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m1.not_result <= sign;
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m1.addend <= (others => sign);
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m1.valid <= '1';
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result(63 downto 0), behave_rt, result("for mullw " & to_hstring(behave_rt)));
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end loop;
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elsif run("Test mulhw") then
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mulhw_loop : for i in 0 to 1000 loop
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ra := rnd.RandSlv(ra'length);
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rb := rnd.RandSlv(rb'length);
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behave_rt := ppc_mulhw(ra, rb);
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m1.data1 <= (others => '0');
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m1.data1(31 downto 0) <= absval(ra(31 downto 0));
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m1.data2 <= (others => '0');
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m1.data2(31 downto 0) <= absval(rb(31 downto 0));
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sign := ra(31) xor rb(31);
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m1.not_result <= sign;
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m1.addend <= (others => sign);
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m1.valid <= '1';
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result(63 downto 32) & m2.result(63 downto 32), behave_rt, result("for mulhw " & to_hstring(behave_rt)));
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end loop;
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elsif run("Test mulhwu") then
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mulhwu_loop : for i in 0 to 1000 loop
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ra := rnd.RandSlv(ra'length);
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rb := rnd.RandSlv(rb'length);
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behave_rt := ppc_mulhwu(ra, rb);
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m1.data1 <= (others => '0');
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m1.data1(31 downto 0) <= ra(31 downto 0);
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m1.data2 <= (others => '0');
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m1.data2(31 downto 0) <= rb(31 downto 0);
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m1.not_result <= '0';
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m1.addend <= (others => '0');
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m1.valid <= '1';
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result(63 downto 32) & m2.result(63 downto 32), behave_rt, result("for mulhwu " & to_hstring(behave_rt)));
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end loop;
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elsif run("Test mulli") then
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mulli_loop : for i in 0 to 1000 loop
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ra := rnd.RandSlv(ra'length);
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si := rnd.RandSlv(si'length);
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behave_rt := ppc_mulli(ra, si);
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m1.data1 <= absval(ra);
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m1.data2 <= (others => '0');
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m1.data2(15 downto 0) <= absval(si);
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sign := ra(63) xor si(15);
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m1.not_result <= sign;
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m1.addend <= (others => sign);
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m1.valid <= '1';
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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check_true(?? m2.valid, result("for valid"));
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check_equal(m2.result(63 downto 0), behave_rt, result("for mulli " & to_hstring(behave_rt)));
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end loop;
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end if;
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end loop;
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test_runner_cleanup(runner);
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wait;
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end process;
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end behave;
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