mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-01-11 23:43:15 +00:00
08c0c4c1b4
This commit also removes the dependencies these testbenches have on VHPIDIRECT. The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists. For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions. The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using the -p option to the run.py script Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
32 lines
679 B
VHDL
32 lines
679 B
VHDL
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
|
|
library osvvm;
|
|
use osvvm.RandomPkg.all;
|
|
|
|
entity random is
|
|
port (
|
|
clk : in std_ulogic;
|
|
data : out std_ulogic_vector(63 downto 0);
|
|
raw : out std_ulogic_vector(63 downto 0);
|
|
err : out std_ulogic
|
|
);
|
|
end entity random;
|
|
|
|
architecture behaviour of random is
|
|
begin
|
|
err <= '0';
|
|
|
|
process(clk)
|
|
variable rand : std_ulogic_vector(63 downto 0);
|
|
variable rnd : RandomPType;
|
|
begin
|
|
if rising_edge(clk) then
|
|
rand := rnd.RandSlv(64);
|
|
data <= rand;
|
|
raw <= rand;
|
|
end if;
|
|
end process;
|
|
end behaviour;
|