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antonblanchard.microwatt/litedram/extras
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Raptor Engineering Development Team fcb783a0fb Extend LiteDRAM VHDL wrapper to allow more than one clock line 
This is necessary for the upcoming Arctic Tern system enablement,
since Arctic Tern uses two DRAM devices and a separate clock line
is routed to each device.  LiteX handles this behavior correctly,
therefore we assume other hardware exists that uses a similar
DRAM clock design.

Updates from Mikey to fix some compile issues.

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
2022-02-23 16:33:08 -06:00
..
fusesoc-add-files.py
litedram: Remove old "VexRiscV" based initializations
2020-06-05 11:23:04 +10:00
litedram-wrapper-l2.vhdl
Extend LiteDRAM VHDL wrapper to allow more than one clock line
2022-02-23 16:33:08 -06:00
sim_dram_verilate.mk
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
sim_litedram_c.cpp
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
sim_litedram.vhdl
Extend LiteDRAM VHDL wrapper to allow more than one clock line
2022-02-23 16:33:08 -06:00
wave_tb.gtkw
litedram: l2: Latency improvements
2020-07-08 16:47:30 +10:00
wave.gtkw
litedram: Add an L2 cache with store queue
2020-06-05 10:33:27 +10:00
wave.opt
litedram: Add an L2 cache with store queue
2020-06-05 10:33:27 +10:00