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antonblanchard.microwatt/litedram/generated
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Matt Johnston 8901e84d8d litedram: Add orangecrab-85-0.2 target 
Parameters are based on
https://github.com/gregdavill/OrangeCrab-test-sw/blob/main/hw/OrangeCrab-bitstream.py
and litex-boards orangecrab.py

rtt_nom and cmd_delay are overridden for OrangeCrab, we do the same here.

Generated with litedram and litex
62abf9c ("litedram_gen: Add block_until_ready port parameter to control blocking behaviour.")
add2746a ("tools/litex_cli: Rename wb to bus.")

Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
2022-01-14 09:36:03 +08:00
..
acorn-cle-215
litedram: disable block_until_ready, regenerate
2022-01-14 08:41:36 +08:00
arty
litedram: disable block_until_ready, regenerate
2022-01-14 08:41:36 +08:00
genesys2
litedram: disable block_until_ready, regenerate
2022-01-14 08:41:36 +08:00
nexys-video
litedram: disable block_until_ready, regenerate
2022-01-14 08:41:36 +08:00
orangecrab-85-0.2
litedram: Add orangecrab-85-0.2 target
2022-01-14 09:36:03 +08:00
sim
litedram: disable block_until_ready, regenerate
2022-01-14 08:41:36 +08:00
wukong-v2
litedram: disable block_until_ready, regenerate
2022-01-14 08:41:36 +08:00