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https://github.com/antonblanchard/microwatt.git
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ca4eb46aea
This makes the 64-bit wishbone buses have the address expressed in units of doublewords (64 bits), and similarly for the 32-bit buses the address is in units of words (32 bits). This is to comply with the wishbone spec. Previously the addresses on the wishbone buses were in units of bytes regardless of the bus data width, which is not correct and caused problems with interfacing with externally-generated logic. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
100 lines
3.4 KiB
VHDL
100 lines
3.4 KiB
VHDL
-- GPIO module for microwatt
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.wishbone_types.all;
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entity gpio is
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generic (
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NGPIO : integer := 32
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);
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port (
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clk : in std_ulogic;
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rst : in std_ulogic;
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-- Wishbone
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wb_in : in wb_io_master_out;
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wb_out : out wb_io_slave_out;
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-- GPIO lines
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gpio_in : in std_ulogic_vector(NGPIO - 1 downto 0);
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gpio_out : out std_ulogic_vector(NGPIO - 1 downto 0);
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-- 1 = output, 0 = input
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gpio_dir : out std_ulogic_vector(NGPIO - 1 downto 0);
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-- Interrupt
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intr : out std_ulogic
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);
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end entity gpio;
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architecture behaviour of gpio is
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constant GPIO_REG_BITS : positive := 5;
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-- Register addresses, matching addr downto 2, so 4 bytes per reg
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constant GPIO_REG_DATA_OUT : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00000";
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constant GPIO_REG_DATA_IN : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00001";
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constant GPIO_REG_DIR : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00010";
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constant GPIO_REG_DATA_SET : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00100";
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constant GPIO_REG_DATA_CLR : std_ulogic_vector(GPIO_REG_BITS-1 downto 0) := "00101";
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-- Current output value and direction
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signal reg_data : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
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signal reg_dirn : std_ulogic_vector(NGPIO - 1 downto 0) := (others => '0');
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signal reg_in1 : std_ulogic_vector(NGPIO - 1 downto 0);
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signal reg_in2 : std_ulogic_vector(NGPIO - 1 downto 0);
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signal wb_rsp : wb_io_slave_out;
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signal reg_out : std_ulogic_vector(NGPIO - 1 downto 0);
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begin
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-- No interrupt facility for now
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intr <= '0';
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gpio_out <= reg_data;
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gpio_dir <= reg_dirn;
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-- Wishbone response
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wb_rsp.ack <= wb_in.cyc and wb_in.stb;
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with wb_in.adr(GPIO_REG_BITS - 1 downto 0) select reg_out <=
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reg_data when GPIO_REG_DATA_OUT,
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reg_in2 when GPIO_REG_DATA_IN,
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reg_dirn when GPIO_REG_DIR,
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(others => '0') when others;
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wb_rsp.dat(wb_rsp.dat'left downto NGPIO) <= (others => '0');
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wb_rsp.dat(NGPIO - 1 downto 0) <= reg_out;
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wb_rsp.stall <= '0';
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regs_rw: process(clk)
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begin
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if rising_edge(clk) then
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wb_out <= wb_rsp;
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reg_in2 <= reg_in1;
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reg_in1 <= gpio_in;
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if rst = '1' then
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reg_data <= (others => '0');
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reg_dirn <= (others => '0');
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wb_out.ack <= '0';
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else
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if wb_in.cyc = '1' and wb_in.stb = '1' and wb_in.we = '1' then
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case wb_in.adr(GPIO_REG_BITS - 1 downto 0) is
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when GPIO_REG_DATA_OUT =>
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reg_data <= wb_in.dat(NGPIO - 1 downto 0);
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when GPIO_REG_DIR =>
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reg_dirn <= wb_in.dat(NGPIO - 1 downto 0);
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when GPIO_REG_DATA_SET =>
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reg_data <= reg_data or wb_in.dat(NGPIO - 1 downto 0);
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when GPIO_REG_DATA_CLR =>
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reg_data <= reg_data and not wb_in.dat(NGPIO - 1 downto 0);
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when others =>
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end case;
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end if;
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end if;
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end if;
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end process;
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end architecture behaviour;
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