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478b787c10
The VUnit log package is a SW style logging framework in VHDL and the check package is an assertion library doing its error reporting with VUnit logging. These testbenches don't use, and do not need, very advanced logging/checking features but the following was possible to improve - Checking equality in VHDL can be quite tedious with a lot of type conversions and long message strings to explain the data received and what was expected. VUnit's check_equal procedure allow comparison between same or similar types and automatically create the error message for you. - The code has report statements used for testbench progress reporting and debugging. These were replaced with the info and debug procedures. info logs are visible by default while debug is not. This means that debug logs don't have to be commented, which they are now, when not used. Instead there is a show procedure making debug messages visible. The show procedure has been commented to hide the debug messages but a more elegant solution is to control visibility from a generic and then set that generic from the command line. I've left this as a TODO but the run script allow you to extend the standard CLI of VUnit to add new options and you can also set generics from the run script. - VUnit log messages are color coded if color codes are supported by the terminal. It makes it quicker to spot messages of different types when there are many log messages. Error messages will always be made visible on the terminal but you must use the -v (verbose) to see other logs. - Some tests have a lot of "metvalue detected" warning messages from the numeric_std package and these clutter the logs when using the -v option. VUnit has a simulator independent option allowing you to suppress those messages. That option has been enabled. Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
524 lines
23 KiB
VHDL
524 lines
23 KiB
VHDL
library vunit_lib;
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context vunit_lib.vunit_context;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.ppc_fx_insns.all;
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library osvvm;
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use osvvm.RandomPkg.all;
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entity divider_tb is
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generic (runner_cfg : string := runner_cfg_default);
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end divider_tb;
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architecture behave of divider_tb is
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signal clk : std_ulogic;
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signal rst : std_ulogic;
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constant clk_period : time := 10 ns;
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signal d1 : Execute1ToDividerType;
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signal d2 : DividerToExecute1Type;
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begin
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divider_0: entity work.divider
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port map (clk => clk, rst => rst, d_in => d1, d_out => d2);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
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variable si: std_ulogic_vector(15 downto 0);
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variable d128: std_ulogic_vector(127 downto 0);
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variable q128: std_ulogic_vector(127 downto 0);
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variable q64: std_ulogic_vector(63 downto 0);
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variable rem32: std_ulogic_vector(31 downto 0);
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variable rnd : RandomPType;
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begin
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rnd.InitSeed(stim_process'path_name);
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test_runner_setup(runner, runner_cfg);
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while test_suite loop
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rst <= '1';
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wait for clk_period;
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rst <= '0';
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d1.is_signed <= '0';
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d1.neg_result <= '0';
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d1.is_extended <= '0';
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d1.is_32bit <= '0';
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d1.is_modulus <= '0';
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d1.valid <= '0';
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if run("Test interface") then
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d1.valid <= '1';
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d1.dividend <= x"0000000010001000";
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d1.divisor <= x"0000000000001111";
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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check_equal(d2.write_reg_data, 16#f001#);
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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d1.valid <= '1';
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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check_equal(d2.write_reg_data, 16#f001#);
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wait for clk_period;
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check_false(?? d2.valid, result("for valid"));
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elsif run("Test divd") then
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divd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"8000000000000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divd(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divd"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divdu") then
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divdu_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divdu(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divdu"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divde") then
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divde_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(signed(d128) / signed(rb));
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if q128(127 downto 63) = x"0000000000000000" & '0' or
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q128(127 downto 63) = x"ffffffffffffffff" & '1' then
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behave_rt := q128(63 downto 0);
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end if;
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divde"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divdeu") then
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divdeu_loop : for vlength in 1 to 8 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_extended <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if unsigned(rb) > unsigned(ra) then
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d128 := ra & x"0000000000000000";
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q128 := std_ulogic_vector(unsigned(d128) / unsigned(rb));
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behave_rt := q128(63 downto 0);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divdeu"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divw") then
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divw_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" and (ra /= x"ffffffff80000000" or rb /= x"ffffffffffffffff") then
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behave_rt := ppc_divw(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divw"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divwu") then
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divwu_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := ppc_divwu(ra, rb);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divwu"));
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end loop;
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end loop;
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end loop;
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elsif run("Test divwe") then
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divwe_loop : for vlength in 1 to 4 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63) xor rb(63);
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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q64 := std_ulogic_vector(signed(ra) / signed(rb));
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if q64(63 downto 31) = x"00000000" & '0' or
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q64(63 downto 31) = x"ffffffff" & '1' then
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behave_rt := x"00000000" & q64(31 downto 0);
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divwe"));
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end if;
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end loop;
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end loop;
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end loop;
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elsif run("Test divweu") then
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divweu_loop : for vlength in 1 to 4 loop
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for dlength in 1 to vlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 32)) & x"00000000";
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_32bit <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if unsigned(rb(31 downto 0)) > unsigned(ra(63 downto 32)) then
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behave_rt := std_ulogic_vector(unsigned(ra) / unsigned(rb));
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for divweu"));
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end loop;
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end loop;
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end loop;
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elsif run("Test modsd") then
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modsd_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63);
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d1.is_modulus <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := std_ulogic_vector(signed(ra) rem signed(rb));
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for modsd"));
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end loop;
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end loop;
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end loop;
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elsif run("Test modud") then
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modud_loop : for dlength in 1 to 8 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra;
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d1.divisor <= rb;
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d1.is_modulus <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
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exit;
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end if;
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end loop;
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check_true(?? d2.valid, result("for valid"));
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behave_rt := (others => '0');
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if rb /= x"0000000000000000" then
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behave_rt := std_ulogic_vector(unsigned(ra) rem unsigned(rb));
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end if;
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check_equal(d2.write_reg_data, behave_rt, result("for modud"));
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end loop;
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end loop;
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end loop;
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elsif run("Test modsw") then
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modsw_loop : for dlength in 1 to 4 loop
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for vlength in 1 to dlength loop
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for i in 0 to 100 loop
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ra := std_ulogic_vector(resize(signed(rnd.RandSlv(dlength * 8)), 64));
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rb := std_ulogic_vector(resize(signed(rnd.RandSlv(vlength * 8)), 64));
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d1.dividend <= ra when ra(63) = '0' else std_ulogic_vector(- signed(ra));
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d1.divisor <= rb when rb(63) = '0' else std_ulogic_vector(- signed(rb));
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d1.is_signed <= '1';
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d1.neg_result <= ra(63);
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d1.is_32bit <= '1';
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d1.is_modulus <= '1';
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d1.valid <= '1';
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wait for clk_period;
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d1.valid <= '0';
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for j in 0 to 66 loop
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wait for clk_period;
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if d2.valid = '1' then
|
|
exit;
|
|
end if;
|
|
end loop;
|
|
check_true(?? d2.valid, result("for valid"));
|
|
|
|
behave_rt := (others => '0');
|
|
if rb /= x"0000000000000000" then
|
|
rem32 := std_ulogic_vector(signed(ra(31 downto 0)) rem signed(rb(31 downto 0)));
|
|
if rem32(31) = '0' then
|
|
behave_rt := x"00000000" & rem32;
|
|
else
|
|
behave_rt := x"ffffffff" & rem32;
|
|
end if;
|
|
end if;
|
|
check_equal(d2.write_reg_data, behave_rt, result("for modsw"));
|
|
end loop;
|
|
end loop;
|
|
end loop;
|
|
|
|
elsif run("Test moduw") then
|
|
moduw_loop : for dlength in 1 to 4 loop
|
|
for vlength in 1 to dlength loop
|
|
for i in 0 to 100 loop
|
|
ra := std_ulogic_vector(resize(unsigned(rnd.RandSlv(dlength * 8)), 64));
|
|
rb := std_ulogic_vector(resize(unsigned(rnd.RandSlv(vlength * 8)), 64));
|
|
|
|
d1.dividend <= ra;
|
|
d1.divisor <= rb;
|
|
d1.is_32bit <= '1';
|
|
d1.is_modulus <= '1';
|
|
d1.valid <= '1';
|
|
|
|
wait for clk_period;
|
|
|
|
d1.valid <= '0';
|
|
for j in 0 to 66 loop
|
|
wait for clk_period;
|
|
if d2.valid = '1' then
|
|
exit;
|
|
end if;
|
|
end loop;
|
|
check_true(?? d2.valid, result("for valid"));
|
|
|
|
behave_rt := (others => '0');
|
|
if rb /= x"0000000000000000" then
|
|
behave_rt := x"00000000" & std_ulogic_vector(unsigned(ra(31 downto 0)) rem unsigned(rb(31 downto 0)));
|
|
end if;
|
|
check_equal(d2.write_reg_data(31 downto 0), behave_rt(31 downto 0), result("for moduw"));
|
|
end loop;
|
|
end loop;
|
|
end loop;
|
|
end if;
|
|
end loop;
|
|
|
|
test_runner_cleanup(runner);
|
|
end process;
|
|
end behave;
|