mirror of
https://github.com/antonblanchard/microwatt.git
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82dacf2c1c
The flash chip on my board is an ISSI IS26LP256P chip. The ISSI chip requires slightly different setup for quad mode from the other brands, but works fine with the existing SPI flash interface logic here. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
346 lines
8.4 KiB
C
346 lines
8.4 KiB
C
#include <unistd.h>
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#include <string.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <stdarg.h>
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#include <stdio.h>
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#include <generated/git.h>
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#include "console.h"
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#include "microwatt_soc.h"
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#include "io.h"
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#include "sdram.h"
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#include "elf64.h"
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#define FLASH_LOADER_USE_MAP
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int _printf(const char *fmt, ...)
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{
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int count;
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char buffer[128];
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va_list ap;
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va_start(ap, fmt);
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count = vsnprintf(buffer, sizeof(buffer), fmt, ap);
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va_end(ap);
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puts(buffer);
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return count;
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}
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void flush_cpu_dcache(void)
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{
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}
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void flush_cpu_icache(void)
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{
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__asm__ volatile ("icbi 0,0; isync" : : : "memory");
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}
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#define SPI_CMD_RDID 0x9f
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#define SPI_CMD_READ 0x03
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#define SPI_CMD_DUAL_FREAD 0x3b
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#define SPI_CMD_QUAD_FREAD 0x6b
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#define SPI_CMD_QUAD_FREAD_4BA 0x6c
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#define SPI_CMD_RDCR 0x35
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#define SPI_CMD_WREN 0x06
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#define SPI_CMD_PP 0x02
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#define SPI_CMD_RDSR 0x05
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#define SPI_CMD_WWR 0x01
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static void fl_cs_on(void)
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{
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writeb(SPI_REG_CTRL_MANUAL_CS, SPI_FCTRL_BASE + SPI_REG_CTRL);
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}
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static void fl_cs_off(void)
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{
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writeb(0, SPI_FCTRL_BASE + SPI_REG_CTRL);
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__asm__ volatile("nop");
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__asm__ volatile("nop");
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__asm__ volatile("nop");
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__asm__ volatile("nop");
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__asm__ volatile("nop");
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}
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static void wait_wip(void)
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{
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for (;;) {
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uint8_t sr;
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fl_cs_on();
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writeb(SPI_CMD_RDSR, SPI_FCTRL_BASE + SPI_REG_DATA);
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sr = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
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fl_cs_off();
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if ((sr & 1) == 0)
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break;
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}
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}
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static void send_wren(void)
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{
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fl_cs_on();
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writeb(SPI_CMD_WREN, SPI_FCTRL_BASE + SPI_REG_DATA);
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fl_cs_off();
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}
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static void check_spansion_quad_mode(void)
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{
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uint8_t cf1;
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writeb(SPI_CMD_RDCR, SPI_FCTRL_BASE + SPI_REG_DATA);
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fl_cs_on();
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writeb(SPI_CMD_RDCR, SPI_FCTRL_BASE + SPI_REG_DATA);
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cf1 = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
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fl_cs_off();
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printf(" Cypress/Spansion (CF1=%02x)", cf1);
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if (cf1 & 0x02)
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return;
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printf(" enabling QUAD");
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send_wren();
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fl_cs_on();
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writeb(SPI_CMD_WWR, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(0x00, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(cf1 | 0x02, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(0, SPI_FCTRL_BASE + SPI_REG_CTRL);
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fl_cs_off();
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wait_wip();
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}
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static uint32_t check_enable_issi_quad(void)
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{
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uint8_t sr;
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/* Read status register to see if quad mode is already enabled */
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fl_cs_on();
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writeb(SPI_CMD_RDSR, SPI_FCTRL_BASE + SPI_REG_DATA);
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sr = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
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fl_cs_off();
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if ((sr & 0x40) == 0) {
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printf(" [enabling quad]");
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send_wren();
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fl_cs_on();
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writeb(SPI_CMD_WWR, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(sr | 0x40, SPI_FCTRL_BASE + SPI_REG_DATA);
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fl_cs_off();
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wait_wip();
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}
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/* Enable quad mode and 4B addresses, 8 dummy cycles */
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return SPI_CMD_QUAD_FREAD_4BA |
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(0x07 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT) |
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SPI_REG_AUT_CFG_MODE_QUAD | SPI_REG_AUTO_CFG_ADDR4 |
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(0x20 << SPI_REG_AUTO_CFG_CSTOUT_SHIFT);
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}
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static bool check_flash(void)
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{
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bool quad = false;
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uint8_t id[3];
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uint32_t autocfg;
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/* default auto mode configuration for quad reads: */
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/* Enable quad mode, 8 dummy clocks, 32 cycles CS timeout */
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autocfg = SPI_CMD_QUAD_FREAD |
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(0x07 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT) |
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SPI_REG_AUT_CFG_MODE_QUAD |
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(0x20 << SPI_REG_AUTO_CFG_CSTOUT_SHIFT);
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fl_cs_on();
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writeb(SPI_CMD_RDID, SPI_FCTRL_BASE + SPI_REG_DATA);
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id[0] = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
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id[1] = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
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id[2] = readb(SPI_FCTRL_BASE + SPI_REG_DATA);
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fl_cs_off();
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printf(" SPI FLASH ID: %02x%02x%02x", id[0], id[1], id[2]);
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if ((id[0] | id[1] | id[2]) == 0 ||
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(id[0] & id[1] & id[2]) == 0xff)
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return false;
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/* Supported flash types for quad mode */
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if (id[0] == 0x01 &&
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(id[1] == 0x02 || id[1] == 0x20 || id[1] == 0x60) &&
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(id[2] == 0x18 || id[2] == 0x19)) {
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check_spansion_quad_mode();
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quad = true;
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}
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if (id[0] == 0x20 && id[1] == 0xba && id[2] == 0x18) {
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printf(" Micron");
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quad = true;
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}
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if (id[0] == 0x9d && (id[1] & ~0x10) == 0x60 &&
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id[2] == 0x19) {
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/* ISSI IS25LP256D or IS25WP256D */
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printf(" ISSI");
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autocfg = check_enable_issi_quad();
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quad = true;
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}
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if (quad) {
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uint32_t cfg;
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printf(" [quad IO mode]");
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/* Preserve the default clock div for the board */
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cfg = readl(SPI_FCTRL_BASE + SPI_REG_AUTO_CFG);
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cfg &= SPI_REG_AUTO_CFG_CKDIV_MASK;
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cfg |= autocfg;
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writel(cfg, SPI_FCTRL_BASE + SPI_REG_AUTO_CFG);
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}
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printf("\n");
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return true;
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}
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static bool fl_read(void *dst, uint32_t offset, uint32_t size)
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{
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uint8_t *d = dst;
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#ifdef FLASH_LOADER_USE_MAP
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memcpy(d, (void *)(unsigned long)(SPI_FLASH_BASE + offset), size);
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#else
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if (size < 1)
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return false;
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fl_cs_on();
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writeb(SPI_CMD_QUAD_FREAD, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(offset >> 16, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(offset >> 8, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(offset, SPI_FCTRL_BASE + SPI_REG_DATA);
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writeb(0x00, SPI_FCTRL_BASE + SPI_REG_DATA);
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while(size--)
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*(d++) = readb(SPI_FCTRL_BASE + SPI_REG_DATA_QUAD);
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fl_cs_off();
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#endif
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return true;
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}
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static unsigned long boot_flash(unsigned int offset)
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{
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Elf64_Ehdr ehdr;
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Elf64_Phdr ph;
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unsigned int i, poff, size, off;
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void *addr;
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printf("Trying flash...\n");
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if (!fl_read(&ehdr, offset, sizeof(ehdr)))
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return -1ul;
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if (!IS_ELF(ehdr) || ehdr.e_ident[EI_CLASS] != ELFCLASS64) {
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printf("Doesn't look like an elf64\n");
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goto dump;
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}
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if (ehdr.e_ident[EI_DATA] != ELFDATA2LSB ||
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ehdr.e_machine != EM_PPC64) {
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printf("Not a ppc64le binary\n");
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goto dump;
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}
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poff = offset + ehdr.e_phoff;
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for (i = 0; i < ehdr.e_phnum; i++) {
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if (!fl_read(&ph, poff, sizeof(ph)))
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goto dump;
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if (ph.p_type != PT_LOAD)
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continue;
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/* XXX Add bound checking ! */
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size = ph.p_filesz;
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addr = (void *)ph.p_vaddr;
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off = offset + ph.p_offset;
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printf("Copy segment %d (0x%x bytes) to %p\n", i, size, addr);
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fl_read(addr, off, size);
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poff += ehdr.e_phentsize;
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}
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printf("Booting from DRAM at %x\n", (unsigned int)ehdr.e_entry);
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flush_cpu_icache();
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return ehdr.e_entry;
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dump:
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printf("HDR: %02x %02x %02x %02x %02x %02x %02x %02x\n",
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ehdr.e_ident[0], ehdr.e_ident[1], ehdr.e_ident[2], ehdr.e_ident[3],
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ehdr.e_ident[4], ehdr.e_ident[5], ehdr.e_ident[6], ehdr.e_ident[7]);
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return -1ul;
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}
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static void boot_sdram(void)
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{
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void *s = (void *)(DRAM_INIT_BASE + 0x6000);
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void *d = (void *)DRAM_BASE;
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int sz = (0x10000 - 0x6000);
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printf("Copying payload to DRAM...\n");
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memcpy(d, s, sz);
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printf("Booting from DRAM...\n");
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flush_cpu_icache();
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}
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uint64_t main(void)
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{
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unsigned long ftr, val;
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unsigned int fl_off = 0;
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bool try_flash = false;
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/* Init the UART */
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console_init();
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printf("\n\nWelcome to Microwatt !\n\n");
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/* TODO: Add core version information somewhere in syscon, possibly
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* extracted from git
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*/
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printf(" Soc signature: %016llx\n",
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(unsigned long long)readq(SYSCON_BASE + SYS_REG_SIGNATURE));
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printf(" Soc features: ");
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ftr = readq(SYSCON_BASE + SYS_REG_INFO);
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if (ftr & SYS_REG_INFO_HAS_UART)
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printf("UART ");
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if (ftr & SYS_REG_INFO_HAS_DRAM)
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printf("DRAM ");
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if (ftr & SYS_REG_INFO_HAS_BRAM)
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printf("BRAM ");
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if (ftr & SYS_REG_INFO_HAS_SPI_FLASH)
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printf("SPIFLASH ");
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if (ftr & SYS_REG_INFO_HAS_LITEETH)
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printf("ETHERNET ");
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if (ftr & SYS_REG_INFO_HAS_LITESDCARD)
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printf("SDCARD ");
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printf("\n");
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if (ftr & SYS_REG_INFO_HAS_BRAM) {
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val = readq(SYSCON_BASE + SYS_REG_BRAMINFO) & SYS_REG_BRAMINFO_SIZE_MASK;
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printf(" BRAM: %ld KB\n", val / 1024);
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}
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if (ftr & SYS_REG_INFO_HAS_DRAM) {
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val = readq(SYSCON_BASE + SYS_REG_DRAMINFO) & SYS_REG_DRAMINFO_SIZE_MASK;
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printf(" DRAM: %ld MB\n", val / (1024 * 1024));
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val = readq(SYSCON_BASE + SYS_REG_DRAMINITINFO);
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printf(" DRAM INIT: %ld KB\n", val / 1024);
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}
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val = readq(SYSCON_BASE + SYS_REG_CLKINFO) & SYS_REG_CLKINFO_FREQ_MASK;
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printf(" CLK: %ld MHz\n", val / 1000000);
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if (ftr & SYS_REG_INFO_HAS_SPI_FLASH) {
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val = readq(SYSCON_BASE + SYS_REG_SPI_INFO);
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try_flash = check_flash();
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fl_off = val & SYS_REG_SPI_INFO_FLASH_OFF_MASK;
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printf(" SPI FLASH OFF: 0x%x bytes\n", fl_off);
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try_flash = true;
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}
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printf("\n");
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if (ftr & SYS_REG_INFO_HAS_DRAM && !ddrctrl_init_done_read()) {
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printf("LiteDRAM built from LiteX %s\n", LITEX_GIT_SHA1);
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sdram_init();
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}
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val = readq(SYSCON_BASE + SYS_REG_CTRL);
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writeq(val & ~SYS_REG_CTRL_ALT_RESET, SYSCON_BASE + SYS_REG_CTRL);
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if (ftr & SYS_REG_INFO_HAS_BRAM) {
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printf("Booting from BRAM...\n");
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return 0;
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}
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if (try_flash) {
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val = boot_flash(fl_off);
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if (val != (unsigned long)-1)
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return val;
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}
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boot_sdram();
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return 0;
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}
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