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e02d8060ed
This adds an 'is_signed' signal to MultiplyInputType to indicate whether the data1 and data2 fields are to be interpreted as signed or unsigned numbers. The 'not_result' field is replaced by a 'subtract' field which provides a more intuitive interface for requesting that the product be subtracted from the addend rather than added, i.e. subtract = 1 gives C - A * B, vs. subtract = 0 giving C + A * B. (Previously the users of the multipliers got the same effect by complementing the addend and setting not_result = 1.) The is_32bit field is removed because it is no longer used now that we have a separate 32-bit multiplier. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
57 lines
1.5 KiB
VHDL
57 lines
1.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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-- Signed 33b x 33b multiplier giving 64-bit product, with no addend,
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-- with fixed 1-cycle latency.
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entity multiply_32s is
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port (
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clk : in std_logic;
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stall : in std_ulogic;
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m_in : in MultiplyInputType;
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m_out : out MultiplyOutputType
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);
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end entity multiply_32s;
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architecture behaviour of multiply_32s is
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type reg_type is record
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valid : std_ulogic;
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data : signed(65 downto 0);
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end record;
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constant reg_type_init : reg_type := (valid => '0', data => (others => '0'));
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signal r, rin : reg_type := reg_type_init;
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begin
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multiply_0: process(clk)
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begin
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if rising_edge(clk) and stall = '0' then
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r <= rin;
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end if;
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end process;
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multiply_1: process(all)
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variable v : reg_type;
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variable d : std_ulogic_vector(63 downto 0);
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variable ov : std_ulogic;
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begin
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v.valid := m_in.valid;
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v.data := signed((m_in.is_signed and m_in.data1(31)) & m_in.data1(31 downto 0)) *
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signed((m_in.is_signed and m_in.data2(31)) & m_in.data2(31 downto 0));
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d := std_ulogic_vector(r.data(63 downto 0));
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ov := (or d(63 downto 31)) and not (and d(63 downto 31));
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m_out.result <= 64x"0" & d;
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m_out.overflow <= ov;
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m_out.valid <= r.valid;
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rin <= v;
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end process;
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end architecture behaviour;
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