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This adds a simple bus that can be mastered from an external system via JTAG, which will be used to hookup various debug modules. It's loosely based on the RiscV model (hence the DMI name). The module currently only supports hooking up to a Xilinx BSCANE2 but it shouldn't be too hard to adapt it to support different TAPs if necessary. The JTAG protocol proper is not exactly the RiscV one at this point, though I might still change it. This comes with some sim variants of Xilinx BSCANE2 and BUFG and a test bench. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
46 lines
1.1 KiB
VHDL
46 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.std_logic_1164.all;
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package vcomponents is
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-- Global JTAG signals. Xilinx implementation hooks that up to
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-- their internal JTAG tap, we just expose them for the testbench
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-- to use. These are used by our BSCANE2 block.
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--
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type glob_jtag_t is record
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reset : std_logic;
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tck : std_logic;
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tdo : std_logic;
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tdi : std_logic;
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tms : std_logic;
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sel : std_logic_vector(4 downto 1);
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capture : std_logic;
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shift : std_logic;
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update : std_logic;
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runtest : std_logic;
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end record glob_jtag_t;
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signal glob_jtag : glob_jtag_t;
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component BSCANE2 is
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generic(jtag_chain: integer);
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port(capture : out std_logic;
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drck : out std_logic;
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reset : out std_logic;
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runtest : out std_logic;
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sel : out std_logic;
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shift : out std_logic;
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tck : out std_logic;
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tdi : out std_logic;
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tms : out std_logic;
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update : out std_logic;
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tdo : in std_logic
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);
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end component BSCANE2;
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component BUFG is
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port(I : in std_logic;
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O : out std_logic
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);
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end component BUFG;
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end package vcomponents;
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