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8e0389b973
This replaces the simple_ram_behavioural and mw_soc_memory modules with a common wishbone_bram_wrapper.vhdl that interfaces the pipelined WB with a lower-level RAM module, along with an FPGA and a sim variants of the latter. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
31 lines
1.4 KiB
VHDL
31 lines
1.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package sim_bram_helpers is
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function behavioural_initialize (filename: String; size: integer) return integer;
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attribute foreign of behavioural_initialize : function is "VHPIDIRECT behavioural_initialize";
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procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier:integer);
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attribute foreign of behavioural_read : procedure is "VHPIDIRECT behavioural_read";
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procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer);
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attribute foreign of behavioural_write : procedure is "VHPIDIRECT behavioural_write";
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end sim_bram_helpers;
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package body sim_bram_helpers is
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function behavioural_initialize (filename: String; size: integer) return integer is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_initialize;
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procedure behavioural_read (val: out std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_read;
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procedure behavioural_write (val: std_ulogic_vector(63 downto 0); addr: std_ulogic_vector(63 downto 0); length: integer; identifier: integer) is
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begin
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assert false report "VHPI" severity failure;
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end behavioural_write;
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end sim_bram_helpers;
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