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8acd5a5607
While verilator finds the correct top level module with the current setup, if we start adding simulation models it can get confused. Explicitly specify the top level module. Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
84 lines
1.3 KiB
C++
84 lines
1.3 KiB
C++
#include <stdlib.h>
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#include "Vtoplevel.h"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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/*
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* Current simulation time
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* This is a 64-bit integer to reduce wrap over issues and
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* allow modulus. You can also use a double, if you wish.
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*/
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vluint64_t main_time = 0;
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/*
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* Called by $time in Verilog
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* converts to double, to match
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* what SystemC does
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*/
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double sc_time_stamp(void)
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{
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return main_time;
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}
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#if VM_TRACE
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VerilatedVcdC *tfp;
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#endif
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void tick(Vtoplevel *top)
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{
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top->ext_clk = 1;
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top->eval();
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#if VM_TRACE
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if (tfp)
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tfp->dump((double) main_time);
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#endif
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main_time++;
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top->ext_clk = 0;
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top->eval();
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#if VM_TRACE
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if (tfp)
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tfp->dump((double) main_time);
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#endif
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main_time++;
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}
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void uart_tx(unsigned char tx);
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unsigned char uart_rx(void);
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int main(int argc, char **argv)
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{
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Verilated::commandArgs(argc, argv);
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// init top verilog instance
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Vtoplevel* top = new Vtoplevel;
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#if VM_TRACE
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// init trace dump
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Verilated::traceEverOn(true);
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tfp = new VerilatedVcdC;
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top->trace(tfp, 99);
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tfp->open("microwatt-verilator.vcd");
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#endif
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// Reset
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top->ext_rst = 0;
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for (unsigned long i = 0; i < 5; i++)
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tick(top);
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top->ext_rst = 1;
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while(!Verilated::gotFinish()) {
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tick(top);
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uart_tx(top->uart0_txd);
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top->uart0_rxd = uart_rx();
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}
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#if VM_TRACE
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tfp->close();
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delete tfp;
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#endif
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delete top;
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}
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