mirror of
https://github.com/antonblanchard/microwatt.git
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21ed730514
This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
158 lines
6.1 KiB
C
158 lines
6.1 KiB
C
#ifndef __MICROWATT_SOC_H
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#define __MICROWATT_SOC_H
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/*
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* Microwatt SoC memory map
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*/
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#define MEMORY_BASE 0x00000000 /* "Main" memory alias, either BRAM or DRAM */
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#define DRAM_BASE 0x40000000 /* DRAM if present */
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#define BRAM_BASE 0x80000000 /* Internal BRAM */
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#define SYSCON_BASE 0xc0000000 /* System control regs */
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#define UART_BASE 0xc0002000 /* UART */
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#define XICS_ICP_BASE 0xc0004000 /* Interrupt controller */
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#define XICS_ICS_BASE 0xc0005000 /* Interrupt controller */
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#define SPI_FCTRL_BASE 0xc0006000 /* SPI flash controller registers */
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#define DRAM_CTRL_BASE 0xc8000000 /* LiteDRAM control registers */
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#define LETH_CSR_BASE 0xc8020000 /* LiteEth CSR registers */
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#define LETH_SRAM_BASE 0xc8030000 /* LiteEth MMIO space */
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#define LSDC_CSR_BASE 0xc8040000 /* LiteSDCard MMIO space */
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#define SPI_FLASH_BASE 0xf0000000 /* SPI Flash memory map */
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#define DRAM_INIT_BASE 0xff000000 /* Internal DRAM init firmware */
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/*
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* Interrupt numbers
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*/
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#define IRQ_UART0 0
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#define IRQ_ETHERNET 1
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/*
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* Register definitions for the syscon registers
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*/
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#define SYS_REG_SIGNATURE 0x00
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#define SYS_REG_INFO 0x08
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#define SYS_REG_INFO_HAS_UART (1ull << 0)
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#define SYS_REG_INFO_HAS_DRAM (1ull << 1)
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#define SYS_REG_INFO_HAS_BRAM (1ull << 2)
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#define SYS_REG_INFO_HAS_SPI_FLASH (1ull << 3)
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#define SYS_REG_INFO_HAS_LITEETH (1ull << 4)
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#define SYS_REG_INFO_HAS_LARGE_SYSCON (1ull << 5)
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#define SYS_REG_INFO_HAS_UART1 (1ull << 6)
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#define SYS_REG_INFO_HAS_ARTB (1ull << 7)
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#define SYS_REG_INFO_HAS_LITESDCARD (1ull << 8)
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#define SYS_REG_BRAMINFO 0x10
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#define SYS_REG_BRAMINFO_SIZE_MASK 0xfffffffffffffull
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#define SYS_REG_DRAMINFO 0x18
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#define SYS_REG_DRAMINFO_SIZE_MASK 0xfffffffffffffull
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#define SYS_REG_CLKINFO 0x20
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#define SYS_REG_CLKINFO_FREQ_MASK 0xffffffffffull
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#define SYS_REG_CTRL 0x28
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#define SYS_REG_CTRL_DRAM_AT_0 (1ull << 0)
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#define SYS_REG_CTRL_CORE_RESET (1ull << 1)
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#define SYS_REG_CTRL_SOC_RESET (1ull << 2)
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#define SYS_REG_DRAMINITINFO 0x30
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#define SYS_REG_SPI_INFO 0x38
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#define SYS_REG_SPI_INFO_FLASH_OFF_MASK 0xffffffff
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#define SYS_REG_UART0_INFO 0x40
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#define SYS_REG_UART1_INFO 0x48
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#define SYS_REG_UART_IS_16550 (1ull << 32)
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/*
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* Register definitions for the potato UART
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*/
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#define POTATO_CONSOLE_TX 0x00
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#define POTATO_CONSOLE_RX 0x08
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#define POTATO_CONSOLE_STATUS 0x10
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#define POTATO_CONSOLE_STATUS_RX_EMPTY 0x01
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#define POTATO_CONSOLE_STATUS_TX_EMPTY 0x02
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#define POTATO_CONSOLE_STATUS_RX_FULL 0x04
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#define POTATO_CONSOLE_STATUS_TX_FULL 0x08
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#define POTATO_CONSOLE_CLOCK_DIV 0x18
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#define POTATO_CONSOLE_IRQ_EN 0x20
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#define POTATO_CONSOLE_IRQ_RX 0x01
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#define POTATO_CONSOLE_IRQ_TX 0x02
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/*
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* Register definitionss for our standard (16550 style) UART
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*/
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#define UART_REG_RX 0x00
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#define UART_REG_TX 0x00
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#define UART_REG_DLL 0x00
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#define UART_REG_IER 0x04
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#define UART_REG_IER_RDI 0x01
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#define UART_REG_IER_THRI 0x02
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#define UART_REG_IER_RLSI 0x04
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#define UART_REG_IER_MSI 0x08
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#define UART_REG_DLM 0x04
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#define UART_REG_IIR 0x08
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#define UART_REG_FCR 0x08
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#define UART_REG_FCR_EN_FIFO 0x01
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#define UART_REG_FCR_CLR_RCVR 0x02
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#define UART_REG_FCR_CLR_XMIT 0x04
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#define UART_REG_FCR_TRIG1 0x00
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#define UART_REG_FCR_TRIG4 0x40
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#define UART_REG_FCR_TRIG8 0x80
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#define UART_REG_FCR_TRIG14 0xc0
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#define UART_REG_LCR 0x0c
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#define UART_REG_LCR_5BIT 0x00
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#define UART_REG_LCR_6BIT 0x01
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#define UART_REG_LCR_7BIT 0x02
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#define UART_REG_LCR_8BIT 0x03
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#define UART_REG_LCR_STOP 0x04
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#define UART_REG_LCR_PAR 0x08
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#define UART_REG_LCR_EVEN_PAR 0x10
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#define UART_REG_LCR_STIC_PAR 0x20
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#define UART_REG_LCR_BREAK 0x40
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#define UART_REG_LCR_DLAB 0x80
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#define UART_REG_MCR 0x10
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#define UART_REG_MCR_DTR 0x01
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#define UART_REG_MCR_RTS 0x02
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#define UART_REG_MCR_OUT1 0x04
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#define UART_REG_MCR_OUT2 0x08
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#define UART_REG_MCR_LOOP 0x10
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#define UART_REG_LSR 0x14
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#define UART_REG_LSR_DR 0x01
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#define UART_REG_LSR_OE 0x02
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#define UART_REG_LSR_PE 0x04
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#define UART_REG_LSR_FE 0x08
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#define UART_REG_LSR_BI 0x10
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#define UART_REG_LSR_THRE 0x20
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#define UART_REG_LSR_TEMT 0x40
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#define UART_REG_LSR_FIFOE 0x80
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#define UART_REG_MSR 0x18
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#define UART_REG_SCR 0x1c
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/*
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* Register definitions for the SPI controller
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*/
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#define SPI_REG_DATA 0x00 /* Byte access: single wire transfer */
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#define SPI_REG_DATA_DUAL 0x01 /* Byte access: dual wire transfer */
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#define SPI_REG_DATA_QUAD 0x02 /* Byte access: quad wire transfer */
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#define SPI_REG_CTRL 0x04 /* Reset and manual mode control */
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#define SPI_REG_CTRL_RESET 0x01 /* reset all registers */
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#define SPI_REG_CTRL_MANUAL_CS 0x02 /* assert CS, enable manual mode */
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#define SPI_REG_CTRL_CKDIV_SHIFT 8 /* clock div */
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#define SPI_REG_CTRL_CKDIV_MASK (0xff << SPI_REG_CTRL_CKDIV_SHIFT)
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#define SPI_REG_AUTO_CFG 0x08 /* Automatic map configuration */
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#define SPI_REG_AUTO_CFG_CMD_SHIFT 0 /* Command to use for reads */
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#define SPI_REG_AUTO_CFG_CMD_MASK (0xff << SPI_REG_AUTO_CFG_CMD_SHIFT)
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#define SPI_REG_AUTO_CFG_DUMMIES_SHIFT 8 /* # dummy cycles */
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#define SPI_REG_AUTO_CFG_DUMMIES_MASK (0x7 << SPI_REG_AUTO_CFG_DUMMIES_SHIFT)
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#define SPI_REG_AUTO_CFG_MODE_SHIFT 11 /* SPI wire mode */
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#define SPI_REG_AUTO_CFG_MODE_MASK (0x3 << SPI_REG_AUTO_CFG_MODE_SHIFT)
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#define SPI_REG_AUT_CFG_MODE_SINGLE (0 << 11)
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#define SPI_REG_AUT_CFG_MODE_DUAL (2 << 11)
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#define SPI_REG_AUT_CFG_MODE_QUAD (3 << 11)
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#define SPI_REG_AUTO_CFG_ADDR4 (1u << 13) /* 3 or 4 addr bytes */
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#define SPI_REG_AUTO_CFG_CKDIV_SHIFT 16 /* clock div */
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#define SPI_REG_AUTO_CFG_CKDIV_MASK (0xff << SPI_REG_AUTO_CFG_CKDIV_SHIFT)
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#define SPI_REG_AUTO_CFG_CSTOUT_SHIFT 24 /* CS timeout */
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#define SPI_REG_AUTO_CFG_CSTOUT_MASK (0x3f << SPI_REG_AUTO_CFG_CSTOUT_SHIFT)
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#endif /* __MICROWATT_SOC_H */
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