github.com/antonblanchard.microwatt
1
0
Fork 0
mirror of https://github.com/antonblanchard/microwatt.git synced 2026-02-17 04:57:11 +00:00
Code Releases Activity
Files
02abb135a89f2a2c6ebbcfbe2d9d7775c2e67f7b
antonblanchard.microwatt/litedram/extras
History
Benjamin Herrenschmidt 02abb135a8 litedram: l2: Add support for more geometries 
Make the DRAM data lines and user port width configurable, also
don't hard wire dependency on the wishbone data width.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
2020-07-08 16:47:30 +10:00
..
fusesoc-add-files.py
litedram: Remove old "VexRiscV" based initializations
2020-06-05 11:23:04 +10:00
litedram-wrapper-l2.vhdl
litedram: l2: Add support for more geometries
2020-07-08 16:47:30 +10:00
sim_dram_verilate.mk
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
sim_litedram_c.cpp
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
sim_litedram.vhdl
litedram: Add simulation support
2020-06-05 10:24:47 +10:00
wave_tb.gtkw
litedram: l2: Latency improvements
2020-07-08 16:47:30 +10:00
wave.gtkw
litedram: Add an L2 cache with store queue
2020-06-05 10:33:27 +10:00
wave.opt
litedram: Add an L2 cache with store queue
2020-06-05 10:33:27 +10:00