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There is a long timing path to generate the ack signal from the L2 cache as it's fully combinational for stores, including signals coming from litedram. Instead, pipeline the store acks. This will introduce a cycle latency but should improve timing. Also the core will eventually be smart enough not to wait for store acks to complete them anyway. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>