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Lars Asplund 08c0c4c1b4 Make core testbenches recognized by VUnit
This commit also removes the dependencies these testbenches have on VHPIDIRECT.
The use of VHPIDIRECT limits the number of available simulators for the project. Rather than using
foreign functions the testbenches can be implemented entirely in VHDL where equivalent functionality exists.
For these testbenches the VHPIDIRECT-based randomization functions were replaced with VHDL-based functions.

The testbenches recognized by VUnit can be executed in parallel threads for better simulation performance using
the -p option to the run.py script

Signed-off-by: Lars Asplund <lars.anders.asplund@gmail.com>
2021-06-09 18:00:53 +02:00

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708 B
Python

from pathlib import Path
from vunit import VUnit
from glob import glob
prj = VUnit.from_argv()
prj.add_osvvm()
root = Path(__file__).parent
lib = prj.add_library("lib")
lib.add_source_files(root / "litedram/extras/*.vhdl")
lib.add_source_files(root / "litedram/generated/sim/*.vhdl")
# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
vhdl_files = glob(str(root / "*.vhdl"))
vhdl_files = [
src_file
for src_file in vhdl_files
if ("xilinx-mult" not in src_file)
and ("foreign_random" not in src_file)
and ("nonrandom" not in src_file)
]
lib.add_source_files(vhdl_files)
unisim = prj.add_library("unisim")
unisim.add_source_files(root / "sim-unisim/*.vhdl")
prj.main()