antonblanchard.microwatt

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History

Paul Mackerras 1b6ee631bc core: Implement LPCR register

This implements the LPCR (Logical Partition Control Register) with 5
read/write bits.  The other 59 bits are read-only; two (HR and UPRT)
read as 1 and the rest as 0.

The bits that are implemented are:
* HAIL - enables taking interrupts with relocation on
* LD - enables large decrementer mode
* HEIC - disables external interrupts when set
* LPES - controls how external interrupts are delivered
* HVICE - does nothing at present since there is no source of
  	  Hypervisor Virtualization Interrupts.

This also fixes a bug where MSR[RI] was getting cleared by the
delivery of hypervisor interrupts.

Signed-off-by: Paul Mackerras <paulus@ozlabs.org>

2025-03-28 20:38:20 +11:00

fmt_log

Implement cfuged, pdepd and pextd

2024-12-20 22:24:31 +11:00

mw_debug

core: Implement LPCR register

2025-03-28 20:38:20 +11:00

bin2hex.py

bin2hex: Make sure to generate little endian files

2020-06-02 19:56:08 +10:00

dependencies.py

uart: Rename sim_uart.vhdl to sim_pp_uart.vhdl