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https://github.com/antonblanchard/microwatt.git
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573b6b4bc4
This changes the SoC interconnect such that the main 64-bit wishbone out of the processor is first split between only 3 slaves (BRAM, DRAM and a general "IO" bus) instead of all the slaves in the SoC. The IO bus leg is then latched and down-converted to 32 bits data width, before going through a second address decoder for the various IO devices. This significantly reduces routing and timing pressure on the main bus, allowing to get rid of frequent timing violations when synthetizing on small'ish FPGAs such as the Artix-7 35T found on the original Arty board. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
30 lines
481 B
C
30 lines
481 B
C
#include <stdint.h>
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#include "microwatt_soc.h"
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#include "io.h"
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#define XICS_XIRR_POLL 0x0
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#define XICS_XIRR 0x4
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#define XICS_RESV 0x8
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#define XICS_MFRR 0xC
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uint8_t xics_read8(int offset)
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{
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return readb(XICS_BASE + offset);
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}
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void xics_write8(int offset, uint8_t val)
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{
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writeb(val, XICS_BASE + offset);
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}
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uint32_t xics_read32(int offset)
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{
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return readl(XICS_BASE + offset);
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}
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void xics_write32(int offset, uint32_t val)
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{
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writel(val, XICS_BASE + offset);
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}
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