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21ed730514
This adds litesdcard.v generated from the litex/litesdcard project, along with logic in top-arty.vhdl to connect it into the system. There is now a DMA wishbone coming in to soc.vhdl which is narrower than the other wishbone masters (it has 32-bit data rather than 64-bit) so there is a widening/narrowing adapter between it and the main wishbone master arbiter. Also, litesdcard generates a non-pipelined wishbone for its DMA connection, which needs to be converted to a pipelined wishbone. We have a latch on both the incoming and outgoing sides of the wishbone in order to help make timing (at the cost of two extra cycles of latency). litesdcard generates an interrupt signal which is wired up to input 3 of the ICS (IRQ 19). Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
57 lines
2.2 KiB
VHDL
57 lines
2.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package wishbone_types is
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--
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-- Main CPU bus. 32-bit address, 64-bit data
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--
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constant wishbone_addr_bits : integer := 32;
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constant wishbone_data_bits : integer := 64;
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constant wishbone_sel_bits : integer := wishbone_data_bits/8;
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subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
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subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
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subtype wishbone_sel_type is std_ulogic_vector(wishbone_sel_bits-1 downto 0);
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type wishbone_master_out is record
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adr : wishbone_addr_type;
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dat : wishbone_data_type;
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sel : wishbone_sel_type;
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cyc : std_ulogic;
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stb : std_ulogic;
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we : std_ulogic;
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end record;
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constant wishbone_master_out_init : wishbone_master_out := (adr => (others => '0'), dat => (others => '0'), cyc => '0', stb => '0', sel => (others => '0'), we => '0');
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type wishbone_slave_out is record
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dat : wishbone_data_type;
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ack : std_ulogic;
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stall : std_ulogic;
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end record;
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constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', stall => '0', others => (others => '0'));
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type wishbone_master_out_vector is array (natural range <>) of wishbone_master_out;
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type wishbone_slave_out_vector is array (natural range <>) of wishbone_slave_out;
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--
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-- IO Bus to a device, 30-bit address, 32-bits data
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--
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type wb_io_master_out is record
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adr : std_ulogic_vector(29 downto 0);
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dat : std_ulogic_vector(31 downto 0);
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sel : std_ulogic_vector(3 downto 0);
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cyc : std_ulogic;
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stb : std_ulogic;
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we : std_ulogic;
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end record;
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constant wb_io_master_out_init : wb_io_master_out := (adr => (others => '0'), dat => (others => '0'),
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sel => "0000", cyc => '0', stb => '0', we => '0');
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type wb_io_slave_out is record
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dat : std_ulogic_vector(31 downto 0);
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ack : std_ulogic;
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stall : std_ulogic;
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end record;
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constant wb_io_slave_out_init : wb_io_slave_out := (ack => '0', stall => '0', others => (others => '0'));
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end package wishbone_types;
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