mirror of
https://github.com/antonblanchard/microwatt.git
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45cd8f4fc3
This extends the register file so it can hold FPR values, and implements the FP loads and stores that do not require conversion between single and double precision. We now have the FP, FE0 and FE1 bits in MSR. FP loads and stores cause a FP unavailable interrupt if MSR[FP] = 0. The FPU facilities are optional and their presence is controlled by the HAS_FPU generic passed down from the top-level board file. It defaults to true for all except the A7-35 boards. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
108 lines
3.2 KiB
VHDL
108 lines
3.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity gpr_hazard is
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generic (
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PIPELINE_DEPTH : natural := 1
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);
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port(
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clk : in std_ulogic;
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busy_in : in std_ulogic;
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deferred : in std_ulogic;
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complete_in : in std_ulogic;
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flush_in : in std_ulogic;
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issuing : in std_ulogic;
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gpr_write_valid_in : in std_ulogic;
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gpr_write_in : in gspr_index_t;
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bypass_avail : in std_ulogic;
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gpr_read_valid_in : in std_ulogic;
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gpr_read_in : in gspr_index_t;
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ugpr_write_valid : in std_ulogic;
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ugpr_write_reg : in gspr_index_t;
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stall_out : out std_ulogic;
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use_bypass : out std_ulogic
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);
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end entity gpr_hazard;
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architecture behaviour of gpr_hazard is
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type pipeline_entry_type is record
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valid : std_ulogic;
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bypass : std_ulogic;
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gpr : gspr_index_t;
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ugpr_valid : std_ulogic;
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ugpr : gspr_index_t;
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end record;
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constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0', gpr => (others => '0'),
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ugpr_valid => '0', ugpr => (others => '0'));
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type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
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constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
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signal r, rin : pipeline_t := pipeline_t_init;
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begin
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gpr_hazard0: process(clk)
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begin
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if rising_edge(clk) then
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r <= rin;
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end if;
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end process;
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gpr_hazard1: process(all)
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variable v : pipeline_t;
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begin
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v := r;
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if complete_in = '1' then
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v(PIPELINE_DEPTH).valid := '0';
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v(PIPELINE_DEPTH).ugpr_valid := '0';
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end if;
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stall_out <= '0';
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use_bypass <= '0';
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if gpr_read_valid_in = '1' then
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loop_0: for i in 0 to PIPELINE_DEPTH loop
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if v(i).valid = '1' and r(i).gpr = gpr_read_in then
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if r(i).bypass = '1' then
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use_bypass <= '1';
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else
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stall_out <= '1';
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end if;
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end if;
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if v(i).ugpr_valid = '1' and r(i).ugpr = gpr_read_in then
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stall_out <= '1';
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end if;
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end loop;
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end if;
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-- XXX assumes PIPELINE_DEPTH = 1
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if busy_in = '0' then
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v(1) := v(0);
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v(0).valid := '0';
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v(0).ugpr_valid := '0';
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end if;
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if deferred = '0' and issuing = '1' then
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v(0).valid := gpr_write_valid_in;
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v(0).bypass := bypass_avail;
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v(0).gpr := gpr_write_in;
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v(0).ugpr_valid := ugpr_write_valid;
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v(0).ugpr := ugpr_write_reg;
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end if;
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if flush_in = '1' then
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v(0).valid := '0';
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v(0).ugpr_valid := '0';
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v(1).valid := '0';
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v(1).ugpr_valid := '0';
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end if;
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-- update registers
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rin <= v;
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end process;
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end;
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