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https://github.com/antonblanchard/microwatt.git
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374f4c536d
This adds code to writeback to format data and test the result against zero for the purpose of setting CR0. The data formatter is able to shift and mask by bytes and do byte reversal and sign extension. It can also put together bytes from two input doublewords to support unaligned loads (including unaligned byte-reversed loads). The data formatter starts with an 8:1 multiplexer that is able to direct any byte of the input to any byte of the output. This lets us rotate the data and simultaneously byte-reverse it. The rotated/reversed data goes to a register for the unaligned cases that overlap two doublewords. Then there is per-byte logic that does trimming, sign extension, and splicing together bytes from a previous input doubleword (stored in data_latched) and the current doubleword. Finally the 64-bit result is tested to set CR0 if rc = 1. This removes the RC logic from the execute2, multiply and divide units, and the shift/mask/byte-reverse/sign-extend logic from loadstore2. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
263 lines
7.3 KiB
VHDL
263 lines
7.3 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.decode_types.all;
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use work.common.all;
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use work.glibc_random.all;
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use work.ppc_fx_insns.all;
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entity multiply_tb is
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end multiply_tb;
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architecture behave of multiply_tb is
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signal clk : std_ulogic;
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constant clk_period : time := 10 ns;
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constant pipeline_depth : integer := 4;
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signal m1 : Decode2ToMultiplyType;
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signal m2 : MultiplyToWritebackType;
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begin
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multiply_0: entity work.multiply
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generic map (PIPELINE_DEPTH => pipeline_depth)
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port map (clk => clk, m_in => m1, m_out => m2);
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clk_process: process
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begin
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clk <= '0';
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wait for clk_period/2;
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clk <= '1';
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wait for clk_period/2;
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end process;
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stim_process: process
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variable ra, rb, rt, behave_rt: std_ulogic_vector(63 downto 0);
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variable si: std_ulogic_vector(15 downto 0);
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begin
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wait for clk_period;
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_L64;
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m1.write_reg <= "10001";
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m1.data1 <= '0' & x"0000000000001000";
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m1.data2 <= '0' & x"0000000000001111";
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m1.rc <= '0';
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wait for clk_period;
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assert m2.valid = '0';
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m1.valid <= '0';
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wait for clk_period;
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assert m2.valid = '0';
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wait for clk_period;
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assert m2.valid = '0';
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wait for clk_period;
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assert m2.valid = '1';
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assert m2.write_reg_enable = '1';
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assert m2.write_reg_nr = "10001";
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assert m2.write_reg_data = x"0000000001111000";
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assert m2.rc = '0';
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wait for clk_period;
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assert m2.valid = '0';
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m1.valid <= '1';
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m1.rc <= '1';
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wait for clk_period;
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assert m2.valid = '0';
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert m2.write_reg_enable = '1';
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assert m2.write_reg_nr = "10001";
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assert m2.write_reg_data = x"0000000001111000";
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assert m2.rc = '1';
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-- test mulld
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mulld_loop : for i in 0 to 1000 loop
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ra := pseudorand(ra'length);
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rb := pseudorand(rb'length);
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behave_rt := ppc_mulld(ra, rb);
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m1.data1 <= '0' & ra;
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m1.data2 <= '0' & rb;
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_L64;
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulld expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhdu
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mulhdu_loop : for i in 0 to 1000 loop
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ra := pseudorand(ra'length);
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rb := pseudorand(rb'length);
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behave_rt := ppc_mulhdu(ra, rb);
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m1.data1 <= '0' & ra;
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m1.data2 <= '0' & rb;
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_H64;
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhdu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhd
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mulhd_loop : for i in 0 to 1000 loop
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ra := pseudorand(ra'length);
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rb := pseudorand(rb'length);
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behave_rt := ppc_mulhd(ra, rb);
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m1.data1 <= ra(63) & ra;
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m1.data2 <= rb(63) & rb;
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_H64;
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhd expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mullw
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mullw_loop : for i in 0 to 1000 loop
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ra := pseudorand(ra'length);
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rb := pseudorand(rb'length);
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behave_rt := ppc_mullw(ra, rb);
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m1.data1 <= (others => ra(31));
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m1.data1(31 downto 0) <= ra(31 downto 0);
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m1.data2 <= (others => rb(31));
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m1.data2(31 downto 0) <= rb(31 downto 0);
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_L64;
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mullw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhw
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mulhw_loop : for i in 0 to 1000 loop
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ra := pseudorand(ra'length);
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rb := pseudorand(rb'length);
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behave_rt := ppc_mulhw(ra, rb);
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m1.data1 <= (others => ra(31));
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m1.data1(31 downto 0) <= ra(31 downto 0);
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m1.data2 <= (others => rb(31));
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m1.data2(31 downto 0) <= rb(31 downto 0);
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_H32;
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhw expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulhwu
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mulhwu_loop : for i in 0 to 1000 loop
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ra := pseudorand(ra'length);
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rb := pseudorand(rb'length);
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behave_rt := ppc_mulhwu(ra, rb);
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m1.data1 <= (others => '0');
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m1.data1(31 downto 0) <= ra(31 downto 0);
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m1.data2 <= (others => '0');
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m1.data2(31 downto 0) <= rb(31 downto 0);
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_H32;
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulhwu expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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-- test mulli
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mulli_loop : for i in 0 to 1000 loop
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ra := pseudorand(ra'length);
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si := pseudorand(si'length);
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behave_rt := ppc_mulli(ra, si);
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m1.data1 <= ra(63) & ra;
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m1.data2 <= (others => si(15));
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m1.data2(15 downto 0) <= si;
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m1.valid <= '1';
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m1.insn_type <= OP_MUL_L64;
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wait for clk_period;
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m1.valid <= '0';
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wait for clk_period * (pipeline_depth-1);
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assert m2.valid = '1';
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assert to_hstring(behave_rt) = to_hstring(m2.write_reg_data)
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report "bad mulli expected " & to_hstring(behave_rt) & " got " & to_hstring(m2.write_reg_data);
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end loop;
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assert false report "end of test" severity failure;
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wait;
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end process;
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end behave;
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