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https://github.com/antonblanchard/microwatt.git
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d7458d5beb
The icache RAM is currently LUT ram not block ram. This massively bloats the icache size. We think this is due to yosys not inferencing the RAM correctly but that's yet to be confirmed. Work around this for now by reducing the default size of the icache RAM for the ECP5 builds. On the ECP5 85K builts, this gets us from 95% down to 76% and helps our CI to pass. Signed-off-by: Michael Neuling <mikey@neuling.org>
90 lines
2.2 KiB
VHDL
90 lines
2.2 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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library work;
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use work.wishbone_types.all;
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entity toplevel is
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generic (
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MEMORY_SIZE : positive := (384*1024);
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RAM_INIT_FILE : string := "firmware.hex";
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RESET_LOW : boolean := true;
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CLK_INPUT : positive := 100000000;
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CLK_FREQUENCY : positive := 100000000;
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HAS_FPU : boolean := true;
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HAS_BTC : boolean := false;
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ICACHE_NUM_LINES : natural := 64;
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LOG_LENGTH : natural := 512;
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DISABLE_FLATTEN_CORE : boolean := false;
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UART_IS_16550 : boolean := true
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);
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port(
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ext_clk : in std_ulogic;
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ext_rst : in std_ulogic;
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-- UART0 signals:
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uart0_txd : out std_ulogic;
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uart0_rxd : in std_ulogic
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);
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end entity toplevel;
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architecture behaviour of toplevel is
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-- Reset signals:
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signal soc_rst : std_ulogic;
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signal pll_rst : std_ulogic;
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-- Internal clock signals:
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signal system_clk : std_ulogic;
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signal system_clk_locked : std_ulogic;
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begin
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reset_controller: entity work.soc_reset
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generic map(
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RESET_LOW => RESET_LOW
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)
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port map(
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ext_clk => ext_clk,
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pll_clk => system_clk,
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pll_locked_in => system_clk_locked,
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ext_rst_in => ext_rst,
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pll_rst_out => pll_rst,
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rst_out => soc_rst
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);
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clkgen: entity work.clock_generator
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generic map(
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CLK_INPUT_HZ => CLK_INPUT,
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CLK_OUTPUT_HZ => CLK_FREQUENCY
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)
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port map(
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ext_clk => ext_clk,
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pll_rst_in => pll_rst,
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pll_clk_out => system_clk,
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pll_locked_out => system_clk_locked
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);
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-- Main SoC
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soc0: entity work.soc
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generic map(
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MEMORY_SIZE => MEMORY_SIZE,
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RAM_INIT_FILE => RAM_INIT_FILE,
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SIM => false,
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CLK_FREQ => CLK_FREQUENCY,
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HAS_FPU => HAS_FPU,
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HAS_BTC => HAS_BTC,
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ICACHE_NUM_LINES => ICACHE_NUM_LINES,
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LOG_LENGTH => LOG_LENGTH,
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DISABLE_FLATTEN_CORE => DISABLE_FLATTEN_CORE,
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UART0_IS_16550 => UART_IS_16550
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)
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port map (
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system_clk => system_clk,
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rst => soc_rst,
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uart0_txd => uart0_txd,
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uart0_rxd => uart0_rxd
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);
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end architecture behaviour;
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