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https://github.com/antonblanchard/microwatt.git
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4c61a71a62
This uses the instruction-doubling machinery to send load with update instructions down to loadstore1 as two separate ops, rather than one op with two destinations. This will help to simplify the value tracking mechanisms. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
107 lines
3.5 KiB
VHDL
107 lines
3.5 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package decode_types is
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type insn_type_t is (OP_ILLEGAL, OP_NOP, OP_ADD,
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OP_AND, OP_ATTN, OP_B, OP_BC, OP_BCREG,
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OP_BPERM, OP_CMP, OP_CMPB, OP_CMPEQB, OP_CMPRB,
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OP_CNTZ, OP_CROP,
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OP_DARN, OP_DCBF, OP_DCBST, OP_DCBT, OP_DCBTST,
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OP_DCBZ, OP_DIV, OP_DIVE, OP_EXTS, OP_EXTSWSLI,
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OP_FPOP, OP_FPOP_I,
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OP_ICBI, OP_ICBT, OP_ISEL, OP_ISYNC,
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OP_LOAD, OP_STORE,
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OP_MCRXRX, OP_MFCR, OP_MFMSR, OP_MFSPR, OP_MOD,
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OP_MTCRF, OP_MTMSRD, OP_MTSPR, OP_MUL_L64,
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OP_MUL_H64, OP_MUL_H32, OP_OR,
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OP_POPCNT, OP_PRTY, OP_RFID,
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OP_RLC, OP_RLCL, OP_RLCR, OP_SC, OP_SETB,
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OP_SHL, OP_SHR,
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OP_SYNC, OP_TLBIE, OP_TRAP,
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OP_XOR,
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OP_BCD, OP_ADDG6S,
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OP_FETCH_FAILED
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);
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type input_reg_a_t is (NONE, RA, RA_OR_ZERO, SPR, CIA, FRA);
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type input_reg_b_t is (NONE, RB, CONST_UI, CONST_SI, CONST_SI_HI, CONST_UI_HI, CONST_LI, CONST_BD,
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CONST_DXHI4, CONST_DS, CONST_DQ, CONST_M1, CONST_SH, CONST_SH32, SPR, FRB);
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type input_reg_c_t is (NONE, RS, RCR, FRC, FRS);
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type output_reg_a_t is (NONE, RT, RA, SPR, FRT);
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type rc_t is (NONE, ONE, RC);
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type carry_in_t is (ZERO, CA, OV, ONE);
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constant SH_OFFSET : integer := 0;
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constant MB_OFFSET : integer := 1;
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constant ME_OFFSET : integer := 1;
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constant SH32_OFFSET : integer := 0;
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constant MB32_OFFSET : integer := 1;
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constant ME32_OFFSET : integer := 2;
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constant FXM_OFFSET : integer := 0;
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constant BO_OFFSET : integer := 0;
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constant BI_OFFSET : integer := 1;
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constant BH_OFFSET : integer := 2;
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constant BF_OFFSET : integer := 0;
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constant L_OFFSET : integer := 1;
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constant TOO_OFFSET : integer := 0;
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type unit_t is (NONE, ALU, LDST, FPU);
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type facility_t is (NONE, FPU);
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type length_t is (NONE, is1B, is2B, is4B, is8B);
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type repeat_t is (NONE, -- instruction is not repeated
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DRSE, -- double RS, endian twist
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DRTE, -- double RT, endian twist
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DUPD); -- update-form load
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type decode_rom_t is record
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unit : unit_t;
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facility : facility_t;
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insn_type : insn_type_t;
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input_reg_a : input_reg_a_t;
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input_reg_b : input_reg_b_t;
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input_reg_c : input_reg_c_t;
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output_reg_a : output_reg_a_t;
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input_cr : std_ulogic;
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output_cr : std_ulogic;
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invert_a : std_ulogic;
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invert_out : std_ulogic;
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input_carry : carry_in_t;
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output_carry : std_ulogic;
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-- load/store signals
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length : length_t;
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byte_reverse : std_ulogic;
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sign_extend : std_ulogic;
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update : std_ulogic;
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reserve : std_ulogic;
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-- multiplier and ALU signals
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is_32bit : std_ulogic;
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is_signed : std_ulogic;
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rc : rc_t;
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lr : std_ulogic;
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sgl_pipe : std_ulogic;
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repeat : repeat_t;
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end record;
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constant decode_rom_init : decode_rom_t := (unit => NONE, facility => NONE,
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insn_type => OP_ILLEGAL, input_reg_a => NONE,
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input_reg_b => NONE, input_reg_c => NONE,
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output_reg_a => NONE, input_cr => '0', output_cr => '0',
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invert_a => '0', invert_out => '0', input_carry => ZERO, output_carry => '0',
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length => NONE, byte_reverse => '0', sign_extend => '0',
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update => '0', reserve => '0', is_32bit => '0',
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is_signed => '0', rc => NONE, lr => '0', sgl_pipe => '0', repeat => NONE);
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end decode_types;
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package body decode_types is
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end decode_types;
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