Boris Shingarov 679c547e5f fpga: Add support for Genesys2 ...

Signed-off-by: Boris Shingarov <shingarov@labware.com>

2020-08-07 15:42:28 +10:00

..

sdram_init

litedram: Update generator to work with latest LiteX

2020-07-08 17:32:21 +10:00

acorn-cle-215.yml

acorn: Add support for the Acorn CLE 215+

2020-08-07 15:42:07 +10:00

arty.yml

litedram: Remove old "VexRiscV" based initializations

2020-06-05 11:23:04 +10:00

dram-init-mem.vhdl

litedram: Update generator to work with latest LiteX

2020-07-08 17:32:21 +10:00

generate.py

acorn: Add support for the Acorn CLE 215+

2020-08-07 15:42:07 +10:00

genesys2.yml

fpga: Add support for Genesys2

2020-08-07 15:42:28 +10:00

nexys-video.yml

litedram: Remove old "VexRiscV" based initializations

2020-06-05 11:23:04 +10:00

no-init-mem.vhdl

litedram: Split the init memory from the main wrapper

2020-05-25 11:33:09 +10:00

sim.yml

litedram: Remove old "VexRiscV" based initializations

2020-06-05 11:23:04 +10:00