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16 lines
731 B
Tcl
16 lines
731 B
Tcl
## Clock signal 12 MHz
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set_property -dict { PACKAGE_PIN L17 IOSTANDARD LVCMOS33 } [get_ports { ext_clk }];
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create_clock -add -name sys_clk_pin -period 83.33 -waveform {0 41.66} [get_ports {ext_clk}];
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set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { uart0_txd }];
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set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { uart0_rxd }];
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set_property -dict { PACKAGE_PIN A18 IOSTANDARD LVCMOS33 } [get_ports { ext_rst }];
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property CFGBVS VCCO [current_design]
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
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set_property BITSTREAM.CONFIG.CONFIGRATE 33 [current_design]
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set_property CONFIG_MODE SPIx4 [current_design]
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