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antonblanchard.microwatt/asic
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Anton Blanchard 52f2462232 Add arrays for ASIC flow 
Add VHDL wrappers and verilog behaviourals for the cache_ram,
register_file and main_bram arrays.

Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
2022-08-22 14:43:21 +10:00
..
behavioural
Add arrays for ASIC flow
2022-08-22 14:43:21 +10:00
cache_ram.vhdl
Add arrays for ASIC flow
2022-08-22 14:43:21 +10:00
main_bram.vhdl
Add arrays for ASIC flow
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multiply.vhdl
Add arrays for ASIC flow
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register_file.vhdl
Add arrays for ASIC flow
2022-08-22 14:43:21 +10:00