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6dd0b514ac
For now ... it reduces the routing pressure on the FPGA This needs manual adjustment of the address decoder in soc.vhdl, at least until I can figure out how to deal with std_match Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> # Conflicts: # soc.vhdl # Conflicts: # soc.vhdl
30 lines
1.1 KiB
VHDL
30 lines
1.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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package wishbone_types is
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constant wishbone_addr_bits : integer := 32;
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constant wishbone_data_bits : integer := 64;
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constant wishbone_sel_bits : integer := wishbone_data_bits/8;
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subtype wishbone_addr_type is std_ulogic_vector(wishbone_addr_bits-1 downto 0);
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subtype wishbone_data_type is std_ulogic_vector(wishbone_data_bits-1 downto 0);
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subtype wishbone_sel_type is std_ulogic_vector(wishbone_sel_bits-1 downto 0);
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type wishbone_master_out is record
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adr : wishbone_addr_type;
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dat : wishbone_data_type;
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cyc : std_ulogic;
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stb : std_ulogic;
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sel : wishbone_sel_type;
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we : std_ulogic;
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end record;
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constant wishbone_master_out_init : wishbone_master_out := (cyc => '0', stb => '0', we => '0', others => (others => '0'));
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type wishbone_slave_out is record
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dat : wishbone_data_type;
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ack : std_ulogic;
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end record;
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constant wishbone_slave_out_init : wishbone_slave_out := (ack => '0', others => (others => '0'));
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end package wishbone_types;
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