mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-01-13 15:18:09 +00:00
86212dc879
Rather than having update and decode logic for each individual PLRU as well as a register to store the current PLRU state, we now put the PLRU state in a little RAM, which will typically use LUT RAM on FPGAs, and have just a single copy of the logic to calculate the pseudo-LRU way and to update the PLRU state. This logic is in the plrufn module and is just combinatorial logic. A new module was created for this as other parts of the system are still using plru.vhdl. The PLRU RAM in the icache is read asynchronously in the cycle after the cache tag matching is done. At the end of that cycle the PLRU RAM entry is updated if the access was a cache hit, or a victim way is calculated and stored if the access was a cache miss and miss handling is starting in this cycle. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
357 lines
12 KiB
Makefile
357 lines
12 KiB
Makefile
GHDL ?= ghdl
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GHDLFLAGS=--std=08
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CFLAGS=-O3 -Wall
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# Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall
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VERILATOR_FLAGS=-O3 -Wno-fatal -Wno-CASEOVERLAP -Wno-UNOPTFLAT
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VERILATOR_TRACE=0
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ifeq ($(VERILATOR_TRACE),1)
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VERILATOR_FLAGS += --trace
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verilator_extra_link = -Wl,obj_dir/verilated_vcd_c.o
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endif
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# It takes forever to build with optimisation, so disable by default
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#VERILATOR_CFLAGS=-O3
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# some yosys builds have ghdl plugin built in, otherwise need "-m ghdl"
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GHDLSYNTH ?= $(shell ($(YOSYS) -H | grep -q ghdl) || echo -m ghdl)
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YOSYS ?= yosys
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NEXTPNR ?= nextpnr-ecp5
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ECPPACK ?= ecppack
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ECPPROG ?= ecpprog
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OPENOCD ?= openocd
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VUNITRUN ?= python3 ./run.py
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VERILATOR ?= verilator
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DFUUTIL ?= dfu-util
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DFUSUFFIX ?= dfu-suffix
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# We need a version of GHDL built with either the LLVM or gcc backend.
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# Fedora provides this, but other distros may not. Another option is to use
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# the Docker image.
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DOCKER ?= 0
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PODMAN ?= 0
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ifeq ($(DOCKER), 1)
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DOCKERBIN=docker
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USE_DOCKER=1
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endif
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ifeq ($(PODMAN), 1)
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DOCKERBIN=podman
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USE_DOCKER=1
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endif
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ifeq ($(USE_DOCKER), 1)
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PWD = $(shell pwd)
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DOCKERARGS = run --rm -v $(PWD):/src:z -w /src
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GHDL = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 ghdl
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CC = $(DOCKERBIN) $(DOCKERARGS) ghdl/ghdl:buster-llvm-7 gcc
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GHDLSYNTH = -m ghdl
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YOSYS = $(DOCKERBIN) $(DOCKERARGS) hdlc/ghdl:yosys yosys
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NEXTPNR = $(DOCKERBIN) $(DOCKERARGS) hdlc/nextpnr:ecp5 nextpnr-ecp5
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ECPPACK = $(DOCKERBIN) $(DOCKERARGS) hdlc/prjtrellis ecppack
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OPENOCD = $(DOCKERBIN) $(DOCKERARGS) --device /dev/bus/usb hdlc/prog openocd
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VUNITRUN = $(DOCKERBIN) $(DOCKERARGS) ghdl/vunit:llvm python3 ./run.py
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VERILATOR = $(DOCKERBIN) $(DOCKERARGS) verilator/verilator:latest
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endif
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VUNITARGS += -p10
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all = core_tb icache_tb dcache_tb dmi_dtm_tb \
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wishbone_bram_tb soc_reset_tb
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all: $(all)
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# This updates git.vhdl only when needed. Make runs this before doing
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# dependancy checks hence make will only rebuild dependancies if the
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# git status has actually changed.
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$(shell scripts/make_version.sh git.vhdl)
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core_files = decode_types.vhdl common.vhdl wishbone_types.vhdl fetch1.vhdl \
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utils.vhdl plru.vhdl plrufn.vhdl cache_ram.vhdl icache.vhdl \
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predecode.vhdl decode1.vhdl helpers.vhdl insn_helpers.vhdl \
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control.vhdl decode2.vhdl register_file.vhdl \
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cr_file.vhdl crhelpers.vhdl ppc_fx_insns.vhdl rotator.vhdl \
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logical.vhdl countbits.vhdl multiply.vhdl multiply-32s.vhdl divider.vhdl \
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execute1.vhdl loadstore1.vhdl mmu.vhdl dcache.vhdl writeback.vhdl \
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core_debug.vhdl core.vhdl fpu.vhdl pmu.vhdl
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soc_files = wishbone_arbiter.vhdl wishbone_bram_wrapper.vhdl sync_fifo.vhdl \
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wishbone_debug_master.vhdl xics.vhdl syscon.vhdl gpio.vhdl soc.vhdl \
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spi_rxtx.vhdl spi_flash_ctrl.vhdl git.vhdl
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uart_files = $(wildcard uart16550/*.v)
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soc_sim_files = $(core_files) $(soc_files) sim_console.vhdl sim_pp_uart.vhdl sim_bram_helpers.vhdl \
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sim_bram.vhdl sim_jtag_socket.vhdl sim_jtag.vhdl dmi_dtm_xilinx.vhdl \
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sim_16550_uart.vhdl \
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foreign_random.vhdl glibc_random.vhdl glibc_random_helpers.vhdl
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soc_sim_c_files = sim_vhpi_c.c sim_bram_helpers_c.c sim_console_c.c \
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sim_jtag_socket_c.c
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soc_sim_obj_files=$(soc_sim_c_files:.c=.o)
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comma := ,
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soc_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_sim_obj_files))
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unisim_dir = sim-unisim
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unisim_lib = $(unisim_dir)/unisim-obj08.cf
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unisim_lib_files = $(unisim_dir)/BSCANE2.vhdl $(unisim_dir)/BUFG.vhdl \
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$(unisim_dir)/unisim_vcomponents.vhdl
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$(unisim_lib): $(unisim_lib_files)
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$(GHDL) -i --std=08 --work=unisim --workdir=$(unisim_dir) $^
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GHDLFLAGS += -P$(unisim_dir)
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soc_tbs = core_tb icache_tb dcache_tb dmi_dtm_tb wishbone_bram_tb
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soc_flash_tbs = core_flash_tb
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soc_dram_tbs = dram_tb core_dram_tb
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ifneq ($(FLASH_MODEL_PATH),)
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fmf_dir = $(FLASH_MODEL_PATH)/fmf
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fmf_lib = $(fmf_dir)/fmf-obj08.cf
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fmf_lib_files = $(wildcard $(fmf_dir)/*.vhd)
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GHDLFLAGS += -P$(fmf_dir)
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$(fmf_lib): $(fmf_lib_files)
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$(GHDL) -i --std=08 --work=fmf --workdir=$(fmf_dir) $^
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flash_model_files=$(FLASH_MODEL_PATH)/s25fl128s.vhd
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flash_model_files: $(fmf_lib)
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else
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flash_model_files=sim_no_flash.vhdl
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fmf_lib=
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endif
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$(soc_flash_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) $(fmf_lib) $(flash_model_files) %.vhdl
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$(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $(flash_model_files) $@.vhdl $(unisim_files) -e $@
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$(soc_tbs): %: $(soc_sim_files) $(soc_sim_obj_files) $(unisim_lib) %.vhdl
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$(GHDL) -c $(GHDLFLAGS) $(soc_sim_link) $(soc_sim_files) $@.vhdl -e $@
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soc_reset_tb: fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl
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$(GHDL) -c $(GHDLFLAGS) fpga/soc_reset_tb.vhdl fpga/soc_reset.vhdl -e $@
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# LiteDRAM sim
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VERILATOR_ROOT=$(shell verilator -getenv VERILATOR_ROOT 2>/dev/null)
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ifeq (, $(VERILATOR_ROOT))
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$(soc_dram_tbs):
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$(error "Verilator is required to make this target !")
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else
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verilated_dram: litedram/generated/sim/litedram_core.v
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verilator $(VERILATOR_FLAGS) -CFLAGS $(VERILATOR_CFLAGS) -Wno-fatal --cc $<
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make -C obj_dir -f ../litedram/extras/sim_dram_verilate.mk VERILATOR_ROOT=$(VERILATOR_ROOT)
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SIM_DRAM_CFLAGS = -I. -Iobj_dir -Ilitedram/generated/sim -I$(VERILATOR_ROOT)/include -I$(VERILATOR_ROOT)/include/vltstd
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SIM_DRAM_CFLAGS += -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=$(VERILATOR_TRACE) -DVL_PRINTF=printf -faligned-new
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sim_litedram_c.o: litedram/extras/sim_litedram_c.cpp verilated_dram
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$(CC) $(CPPFLAGS) $(SIM_DRAM_CFLAGS) $(CFLAGS) -c $< -o $@
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soc_dram_files = $(core_files) $(soc_files) litedram/extras/litedram-wrapper-l2.vhdl litedram/generated/sim/litedram-initmem.vhdl
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soc_dram_sim_files = $(soc_sim_files) litedram/extras/sim_litedram.vhdl
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soc_dram_sim_obj_files = $(soc_sim_obj_files) sim_litedram_c.o
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dram_link_files=-Wl,obj_dir/Vlitedram_core__ALL.a -Wl,obj_dir/verilated.o $(verilator_extra_link) -Wl,-lstdc++
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soc_dram_sim_link=$(patsubst %,-Wl$(comma)%,$(soc_dram_sim_obj_files)) $(dram_link_files)
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$(soc_dram_tbs): %: $(soc_dram_files) $(soc_dram_sim_files) $(soc_dram_sim_obj_files) $(flash_model_files) $(unisim_lib) $(fmf_lib) %.vhdl
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$(GHDL) -c $(GHDLFLAGS) $(soc_dram_sim_link) $(soc_dram_files) $(soc_dram_sim_files) $(flash_model_files) $@.vhdl -e $@
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endif
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# Hello world
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MEMORY_SIZE ?=8192
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RAM_INIT_FILE ?=hello_world/hello_world.hex
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# Micropython
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#MEMORY_SIZE=393216
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#RAM_INIT_FILE=micropython/firmware.hex
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FPGA_TARGET ?= ORANGE-CRAB-0.21
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# FIXME: icache RAMs aren't being inferrenced as block RAMs on ECP5
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# with yosys, so make it smaller for now as a workaround.
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ICACHE_NUM_LINES=4
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clkgen=fpga/clk_gen_ecp5.vhd
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toplevel=fpga/top-generic.vhdl
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dmi_dtm=dmi_dtm_dummy.vhdl
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LITEDRAM_GHDL_ARG=
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# OrangeCrab with ECP85 (original v0.0 with UM5G-85 chip)
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ifeq ($(FPGA_TARGET), ORANGE-CRAB)
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RESET_LOW=true
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CLK_INPUT=48000000
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CLK_FREQUENCY=48000000
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LPF=constraints/orange-crab.lpf
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PACKAGE=CSFBGA285
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NEXTPNR_FLAGS=--um5g-85k --freq 48
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OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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ECP_FLASH_OFFSET=0x80000
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endif
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# OrangeCrab with ECP85 (v0.21)
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ifeq ($(FPGA_TARGET), ORANGE-CRAB-0.21)
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RESET_LOW=true
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CLK_INPUT=48000000
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CLK_FREQUENCY=48000000
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LPF=constraints/orange-crab-0.2.lpf
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PACKAGE=CSFBGA285
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NEXTPNR_FLAGS=--85k --speed 8 --freq 48 --timing-allow-fail --ignore-loops
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OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg
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DFU_VENDOR=1209
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DFU_PRODUCT=5af0
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ECP_FLASH_OFFSET=0x80000
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toplevel=fpga/top-orangecrab0.2.vhdl
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litedram_target=orangecrab-85-0.2
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soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v
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dmi_dtm=dmi_dtm_ecp5.vhdl
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endif
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# ECP5-EVN
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ifeq ($(FPGA_TARGET), ECP5-EVN)
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RESET_LOW=true
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CLK_INPUT=12000000
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CLK_FREQUENCY=40000000
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LPF=constraints/ecp5-evn.lpf
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PACKAGE=CABGA381
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NEXTPNR_FLAGS=--um5g-85k --freq 40
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OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
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OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
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endif
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ifneq ($(litedram_target),)
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soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
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litedram/generated/$(litedram_target)/litedram-initmem.vhdl
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soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v
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LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=true
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endif
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GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
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-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
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$(LITEDRAM_GHDL_ARG)
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ifeq ($(FPGA_TARGET), verilator)
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RESET_LOW=true
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CLK_INPUT=50000000
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CLK_FREQUENCY=50000000
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clkgen=fpga/clk_gen_bypass.vhd
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endif
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fpga_files = fpga/soc_reset.vhdl \
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fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
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nonrandom.vhdl
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synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
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microwatt.json: $(synth_files) $(RAM_INIT_FILE)
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$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)"
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microwatt.v: $(synth_files) $(RAM_INIT_FILE)
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$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"
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microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c
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$(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel
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@cp -f obj_dir/microwatt-verilator microwatt-verilator
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microwatt_out.config: microwatt.json $(LPF)
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$(NEXTPNR) --json $< --lpf $(LPF) --textcfg $@.tmp $(NEXTPNR_FLAGS) --package $(PACKAGE)
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mv -f $@.tmp $@
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microwatt.bit: microwatt_out.config
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$(ECPPACK) --compress --freq 38.8 --svf microwatt.svf $< $@
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microwatt.svf: microwatt.bit
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prog: microwatt.svf
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$(OPENOCD) -f $(OPENOCD_JTAG_CONFIG) -f $(OPENOCD_DEVICE_CONFIG) -c "transport select jtag; init; svf $<; exit"
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microwatt.dfu: microwatt.bit
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cp $< $@.tmp
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$(DFUSUFFIX) -v $(DFU_VENDOR) -p $(DFU_PRODUCT) -a $@.tmp
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mv $@.tmp $@
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dfuprog: microwatt.dfu
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$(DFUUTIL) -a 0 -D $<
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ecpprog: microwatt.bit
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$(ECPPROG) -S $<
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ecpflash: microwatt.bit
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test -n "$(ECP_FLASH_OFFSET)" || (echo Error: No ECP_FLASH_OFFSET defined for target; exit 1)
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$(ECPPROG) -o $(ECP_FLASH_OFFSET) $<
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tests = $(sort $(patsubst tests/%.out,%,$(wildcard tests/*.out)))
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tests_console = $(sort $(patsubst tests/%.console_out,%,$(wildcard tests/*.console_out)))
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tests_console: $(tests_console)
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check_vunit:
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$(VUNITRUN) $(VUNITARGS)
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check: $(tests) tests_console test_micropython test_micropython_long tests_unit
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check_light: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 test_micropython test_micropython_long tests_console tests_unit
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$(tests): core_tb
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@./scripts/run_test.sh $@
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$(tests_console): core_tb
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@./scripts/run_test_console.sh $@
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test_micropython: core_tb
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@./scripts/test_micropython.py
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test_micropython_verilator: microwatt-verilator
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@./scripts/test_micropython_verilator.py
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test_micropython_long: core_tb
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@./scripts/test_micropython_long.py
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test_micropython_verilator_long: microwatt-verilator
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@./scripts/test_micropython_verilator_long.py
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tests_soc_tb = $(patsubst %_tb,%_tb_test,$(soc_tbs))
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%_test: %
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./$< --assert-level=error > /dev/null
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tests_soc: $(tests_soc_tb)
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# FIXME SOC tests have bit rotted, so disable for now
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#tests_unit: tests_soc
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TAGS:
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find . -name '*.vhdl' | xargs ./scripts/vhdltags
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.PHONY: TAGS
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_clean:
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rm -f *.o *.cf $(all)
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rm -f fpga/*.o fpga/*.cf
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rm -f sim-unisim/*.o sim-unisim/*.cf
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rm -f litedram/extras/*.o
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rm -f TAGS
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rm -f scripts/mw_debug/*.o
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rm -f scripts/mw_debug/mw_debug
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rm -f microwatt.bin microwatt.json microwatt.svf microwatt_out.config
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rm -f microwatt.v microwatt-verilator
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rm -f git.vhdl
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rm -rf obj_dir/
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clean: _clean
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make -f scripts/mw_debug/Makefile clean
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make -f hello_world/Makefile clean
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distclean: _clean
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rm -f *~ fpga/*~ lib/*~ console/*~ include/*~
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rm -rf litedram/build
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rm -f litedram/extras/*~
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rm -f litedram/gen-src/*~
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rm -f litedram/gen-src/sdram_init/*~
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make -f scripts/mw_debug/Makefile distclean
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make -f hello_world/Makefile distclean
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.PHONY: all prog check check_light clean distclean
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.PRECIOUS: microwatt.json microwatt_out.config microwatt.bit
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