mirror of
https://github.com/antonblanchard/microwatt.git
synced 2026-01-13 15:18:09 +00:00
86212dc879
Rather than having update and decode logic for each individual PLRU as well as a register to store the current PLRU state, we now put the PLRU state in a little RAM, which will typically use LUT RAM on FPGAs, and have just a single copy of the logic to calculate the pseudo-LRU way and to update the PLRU state. This logic is in the plrufn module and is just combinatorial logic. A new module was created for this as other parts of the system are still using plru.vhdl. The PLRU RAM in the icache is read asynchronously in the cycle after the cache tag matching is done. At the end of that cycle the PLRU RAM entry is updated if the access was a cache hit, or a victim way is calculated and stored if the access was a cache miss and miss handling is starting in this cycle. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
591 lines
15 KiB
Plaintext
591 lines
15 KiB
Plaintext
CAPI=2:
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name : ::microwatt:0
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filesets:
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core:
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files:
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- decode_types.vhdl
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- wishbone_types.vhdl
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- common.vhdl
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- fetch1.vhdl
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- predecode.vhdl
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- decode1.vhdl
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- helpers.vhdl
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- decode2.vhdl
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- register_file.vhdl
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- cr_file.vhdl
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- crhelpers.vhdl
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- ppc_fx_insns.vhdl
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- sim_console.vhdl
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- logical.vhdl
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- countbits.vhdl
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- control.vhdl
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- execute1.vhdl
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- fpu.vhdl
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- loadstore1.vhdl
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- mmu.vhdl
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- dcache.vhdl
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- divider.vhdl
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- rotator.vhdl
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- pmu.vhdl
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- writeback.vhdl
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- insn_helpers.vhdl
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- core.vhdl
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- icache.vhdl
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- plru.vhdl
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- plrufn.vhdl
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- cache_ram.vhdl
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- core_debug.vhdl
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- utils.vhdl
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file_type : vhdlSource-2008
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soc:
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files:
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- wishbone_arbiter.vhdl
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- wishbone_debug_master.vhdl
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- wishbone_bram_wrapper.vhdl
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- soc.vhdl
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- xics.vhdl
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- gpio.vhdl
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- syscon.vhdl
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- sync_fifo.vhdl
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- spi_rxtx.vhdl
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- spi_flash_ctrl.vhdl
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- git.vhdl
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file_type : vhdlSource-2008
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fpga:
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files:
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- fpga/main_bram.vhdl
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- fpga/soc_reset.vhdl
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- fpga/pp_fifo.vhd
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- fpga/pp_soc_uart.vhd
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- fpga/pp_utilities.vhd
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- fpga/firmware.hex : {copyto : firmware.hex, file_type : user}
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file_type : vhdlSource-2008
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xilinx_specific:
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files:
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- xilinx-mult.vhdl : {file_type : vhdlSource-2008}
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- xilinx-mult-32s.vhdl : {file_type : vhdlSource-2008}
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- fpga/fpga-random.vhdl : {file_type : vhdlSource-2008}
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- fpga/fpga-random.xdc : {file_type : xdc}
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debug_xilinx:
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files:
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- dmi_dtm_xilinx.vhdl : {file_type : vhdlSource-2008}
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debug_dummy:
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files:
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- dmi_dtm_dummy.vhdl : {file_type : vhdlSource-2008}
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nexys_a7:
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files:
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- fpga/nexys_a7.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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- fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
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nexys_video:
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files:
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- fpga/nexys-video.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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- fpga/top-nexys-video.vhdl : {file_type : vhdlSource-2008}
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acorn_cle_215:
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files:
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- fpga/acorn-cle-215.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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- fpga/top-acorn-cle-215.vhdl : {file_type : vhdlSource-2008}
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genesys2:
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files:
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- fpga/genesys2.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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- fpga/top-genesys2.vhdl : {file_type : vhdlSource-2008}
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arty_a7:
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files:
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- fpga/arty_a7.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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- fpga/top-arty.vhdl : {file_type : vhdlSource-2008}
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antmicro-artix-dc-scm:
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files:
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- fpga/antmicro_artix_dc_scm.xdc: {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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- fpga/top-antmicro-artix-dc-scm.vhdl : {file_type : vhdlSource-2008}
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wukong-v2:
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files:
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- fpga/wukong-v2.xdc : {file_type : xdc}
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- fpga/clk_gen_plle2.vhd : {file_type : vhdlSource-2008}
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- fpga/top-wukong-v2.vhdl : {file_type : vhdlSource-2008}
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cmod_a7-35:
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files:
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- fpga/cmod_a7-35.xdc : {file_type : xdc}
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- fpga/clk_gen_mcmm.vhd : {file_type : vhdlSource-2008}
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- fpga/top-generic.vhdl : {file_type : vhdlSource-2008}
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litedram:
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depend : [":microwatt:litedram"]
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liteeth:
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depend : [":microwatt:liteeth"]
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litesdcard:
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depend : [":microwatt:litesdcard"]
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uart16550:
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depend : ["::uart16550"]
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targets:
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nexys_a7:
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default_tool: vivado
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filesets: [core, nexys_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
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generate: [git_hash]
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parameters :
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- memory_size
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- ram_init_file
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- clk_input
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- clk_frequency
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- disable_flatten_core
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- log_length=2048
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- uart_is_16550
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- has_fpu
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- has_btc
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tools:
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vivado: {part : xc7a100tcsg324-1}
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toplevel : toplevel
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acorn-cle-215-nodram:
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default_tool: vivado
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filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
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generate: [git_hash]
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parameters :
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- memory_size
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- ram_init_file
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- clk_input
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- clk_frequency
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- disable_flatten_core
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- spi_flash_offset=10485760
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- log_length=2048
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- uart_is_16550
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tools:
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vivado: {part : xc7a200tsbg484-2}
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toplevel : toplevel
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genesys2-nodram:
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default_tool: vivado
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filesets: [core, genesys2, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
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parameters :
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- memory_size
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- ram_init_file
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- clk_frequency
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- use_litedram=false
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- no_bram=false
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- disable_flatten_core
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- spi_flash_offset=10485760
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- log_length=2048
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- uart_is_16550=false
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generate: [git_hash]
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tools:
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vivado: {part : xc7k325tffg900-2}
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toplevel : toplevel
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acorn-cle-215:
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default_tool: vivado
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filesets: [core, acorn_cle_215, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
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parameters :
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- memory_size
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- ram_init_file
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- use_litedram=true
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- disable_flatten_core
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- no_bram
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- spi_flash_offset=10485760
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- log_length=2048
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- uart_is_16550
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generate: [litedram_acorn_cle_215, git_hash]
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tools:
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vivado: {part : xc7a200tsbg484-2}
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toplevel : toplevel
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genesys2:
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default_tool: vivado
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filesets: [core, genesys2, soc, fpga, debug_xilinx, litedram, uart16550, xilinx_specific]
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parameters :
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- memory_size
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- ram_init_file
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- use_litedram=true
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- disable_flatten_core
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- no_bram
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- spi_flash_offset=10485760
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- log_length=2048
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- uart_is_16550=false
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generate: [litedram_genesys2, git_hash]
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tools:
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vivado: {part : xc7k325tffg900-2}
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toplevel : toplevel
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nexys_video-nodram:
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default_tool: vivado
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filesets: [core, nexys_video, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
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parameters :
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- memory_size
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- ram_init_file
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- clk_input
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- clk_frequency
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- disable_flatten_core
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- spi_flash_offset=10485760
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- log_length=2048
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- uart_is_16550
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- has_fpu
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- has_btc
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generate: [git_hash]
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tools:
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vivado: {part : xc7a200tsbg484-1}
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toplevel : toplevel
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nexys_video:
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default_tool: vivado
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filesets: [core, nexys_video, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
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parameters:
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- memory_size
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- ram_init_file
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- use_litedram=true
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- use_liteeth=true
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- use_litesdcard=true
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- disable_flatten_core
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- no_bram
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- spi_flash_offset=10485760
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- log_length=2048
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- uart_is_16550
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- has_fpu
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- has_btc
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generate: [litedram_nexys_video, liteeth_nexys_video, litesdcard_nexys_video, git_hash]
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tools:
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vivado: {part : xc7a200tsbg484-1}
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toplevel : toplevel
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arty_a7-35-nodram:
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default_tool: vivado
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filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
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parameters :
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- memory_size
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- ram_init_file
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- clk_input
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- clk_frequency
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- disable_flatten_core
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- spi_flash_offset=3145728
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- log_length=512
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- uart_is_16550
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- has_uart1
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- has_fpu=false
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- has_btc=false
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- use_litesdcard
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generate: [git_hash]
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tools:
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vivado: {part : xc7a35ticsg324-1L}
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toplevel : toplevel
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arty_a7-35:
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default_tool: vivado
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filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
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parameters :
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- memory_size
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- ram_init_file
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- use_litedram=true
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- use_liteeth=true
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- use_litesdcard
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- disable_flatten_core
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- no_bram
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- spi_flash_offset=3145728
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- log_length=512
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- uart_is_16550
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- has_uart1
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- has_fpu=false
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- has_btc=false
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generate: [litedram_arty, liteeth_arty, litesdcard_arty, git_hash]
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tools:
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vivado: {part : xc7a35ticsg324-1L}
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toplevel : toplevel
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arty_a7-100-nodram:
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default_tool: vivado
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filesets: [core, arty_a7, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
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parameters :
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- memory_size
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- ram_init_file
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- clk_input
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- clk_frequency
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- disable_flatten_core
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- spi_flash_offset=4194304
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- log_length=2048
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- uart_is_16550
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- has_uart1
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- has_fpu
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- has_btc
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- use_litesdcard
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generate: [git_hash]
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tools:
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vivado: {part : xc7a100ticsg324-1L}
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toplevel : toplevel
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arty_a7-100:
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default_tool: vivado
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filesets: [core, arty_a7, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
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parameters:
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- memory_size
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- ram_init_file
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- use_litedram=true
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- use_liteeth=true
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- use_litesdcard
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- disable_flatten_core
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- no_bram
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- spi_flash_offset=4194304
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- log_length=2048
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- uart_is_16550
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- has_uart1
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- has_fpu
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- has_btc
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generate: [litedram_arty, liteeth_arty, litesdcard_arty, git_hash]
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tools:
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vivado: {part : xc7a100ticsg324-1L}
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toplevel : toplevel
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antmicro-artix-dc-scm:
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default_tool: vivado
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filesets: [core, antmicro-artix-dc-scm, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific]
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parameters :
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- memory_size
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- ram_init_file
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- use_litedram=true
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- use_liteeth=true
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- clk_input
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- clk_frequency
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- disable_flatten_core
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- no_bram
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- log_length=2048
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- uart_is_16550
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- has_uart1
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- has_fpu
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- has_btc
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generate: [litedram_nexys_video, liteeth_nexys_video, git_hash]
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tools:
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vivado: {part : xc7a100tfgg484-1}
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toplevel : toplevel
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wukong-v2-a100t-nodram:
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default_tool: vivado
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filesets: [core, wukong-v2, soc, fpga, debug_xilinx, uart16550, xilinx_specific, litesdcard]
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parameters:
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- memory_size
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- ram_init_file
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- use_litedram=false
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- use_liteeth=false
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- use_litesdcard=true
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- disable_flatten_core
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- spi_flash_offset=4194304
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- clk_frequency=100000000
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- log_length=2048
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- uart_is_16550
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- has_fpu
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- has_btc
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generate: [litesdcard_wukong-v2, git_hash]
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tools:
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|
vivado: {part : xc7a100tfgg676-1}
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toplevel : toplevel
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|
wukong-v2-a100t:
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default_tool: vivado
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filesets: [core, wukong-v2, soc, fpga, debug_xilinx, litedram, liteeth, uart16550, xilinx_specific, litesdcard]
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|
parameters:
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|
- memory_size=0
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- ram_init_file
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- use_litedram=true
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- use_liteeth=true
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|
- use_litesdcard=true
|
|
- disable_flatten_core
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|
- no_bram=true
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|
- spi_flash_offset=4194304
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- log_length=0
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- uart_is_16550
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- has_fpu
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- has_btc
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generate: [litedram_wukong-v2, liteeth_wukong-v2, litesdcard_wukong-v2, git_hash]
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|
tools:
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|
vivado: {part : xc7a100tfgg676-1}
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toplevel : toplevel
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|
|
|
cmod_a7-35:
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default_tool: vivado
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filesets: [core, cmod_a7-35, soc, fpga, debug_xilinx, uart16550, xilinx_specific]
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parameters :
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|
- memory_size
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- ram_init_file
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- reset_low=false
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- clk_input=12000000
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- clk_frequency
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- disable_flatten_core
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|
- log_length=512
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- uart_is_16550
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|
- has_fpu=false
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- has_btc=false
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generate: [git_hash]
|
|
tools:
|
|
vivado: {part : xc7a35tcpg236-1}
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toplevel : toplevel
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synth:
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filesets: [core, soc, xilinx_specific]
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generate: [git_hash]
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|
tools:
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|
vivado: {pnr : none}
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toplevel: core
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generators:
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git_hash_gen:
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command: scripts/make_version_fusesoc.py
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generate:
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git_hash:
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generator : git_hash_gen
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litedram_arty:
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generator: litedram_gen
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parameters: {board : arty}
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liteeth_arty:
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generator: liteeth_gen
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parameters: {board : arty}
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litesdcard_arty:
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generator: litesdcard_gen
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parameters: {vendor : xilinx}
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litesdcard_nexys_video:
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generator: litesdcard_gen
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parameters: {vendor : xilinx}
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litedram_nexys_video:
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generator: litedram_gen
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parameters: {board : nexys-video}
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liteeth_nexys_video:
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generator: liteeth_gen
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parameters: {board : nexys-video}
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litedram_acorn_cle_215:
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generator: litedram_gen
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parameters: {board : acorn-cle-215}
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litedram_genesys2:
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generator: litedram_gen
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parameters: {board : genesys2}
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litedram_wukong-v2:
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generator: litedram_gen
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parameters: {board : wukong-v2}
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liteeth_wukong-v2:
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generator: liteeth_gen
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parameters: {board : wukong-v2}
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litesdcard_wukong-v2:
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generator: litesdcard_gen
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parameters: {vendor : xilinx}
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parameters:
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memory_size:
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datatype : int
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description : On-chip memory size (bytes). If no_bram is set, this is the size carved out for the DRAM payload
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paramtype : generic
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default : 16384
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ram_init_file:
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datatype : file
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description : Initial on-chip RAM contents
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paramtype : generic
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reset_low:
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datatype : bool
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description : External reset button polarity
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paramtype : generic
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clk_input:
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datatype : int
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description : Clock input frequency in HZ (for top-generic based boards)
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paramtype : generic
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default : 100000000
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clk_frequency:
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datatype : int
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description : Generated system clock frequency in HZ (for top-generic based boards)
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paramtype : generic
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default : 100000000
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has_fpu:
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datatype : bool
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description : Include a floating-point unit in the core
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paramtype : generic
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default : true
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has_btc:
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datatype : bool
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description : Include a branch target cache in the core
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paramtype : generic
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default : true
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disable_flatten_core:
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datatype : bool
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description : Prevent Vivado from flattening the main core components
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paramtype : generic
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default : false
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use_litedram:
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datatype : bool
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description : Use liteDRAM
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paramtype : generic
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default : false
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use_liteeth:
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datatype : bool
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description : Use liteEth
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paramtype : generic
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default : false
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use_litesdcard:
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datatype : bool
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description : Use LiteSDCard
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paramtype : generic
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default : false
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uart_is_16550:
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datatype : bool
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description : Use 16550-compatible UART from OpenCores
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paramtype : generic
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default : true
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has_uart1:
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datatype : bool
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description : Enable second UART (always 16550-compatible)
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paramtype : generic
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default : false
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no_bram:
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datatype : bool
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description : No internal block RAM (only DRAM and init code carrying payload)
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paramtype : generic
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default : false
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spi_flash_offset:
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datatype : int
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description : Offset (in bytes) in the SPI flash of the code payload to run
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paramtype : generic
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log_length:
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datatype : int
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description : Length of the core log buffer in entries (32 bytes each)
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paramtype : generic
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