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antonblanchard.microwatt
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57ad7effededb073200ef8710e81ffbd3e4156e8
antonblanchard.microwatt
/
litedram
/
gen-src
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Michael Neuling
57604c1a6e
Merge pull request
#213
from ozbenh/uart16550
...
Add support for standard 16550 style UART
2020-06-29 12:19:06 +10:00
..
sdram_init
Merge pull request
#213
from ozbenh/uart16550
2020-06-29 12:19:06 +10:00
arty.yml
litedram: Remove old "VexRiscV" based initializations
2020-06-05 11:23:04 +10:00
dram-init-mem.vhdl
litedram: Fix DRAM init mem using too many address bits
2020-06-10 13:10:57 +10:00
generate.py
litedram: Remove old "VexRiscV" based initializations
2020-06-05 11:23:04 +10:00
nexys-video.yml
litedram: Remove old "VexRiscV" based initializations
2020-06-05 11:23:04 +10:00
no-init-mem.vhdl
litedram: Split the init memory from the main wrapper
2020-05-25 11:33:09 +10:00
sim.yml
litedram: Remove old "VexRiscV" based initializations
2020-06-05 11:23:04 +10:00
