mirror of
https://github.com/antonblanchard/microwatt.git
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9880fc7435
This puts the logic that selects which bits of the multiplier result get written into the destination GPR into execute1, moved out from multiply. The multiplier is now expected to do an unsigned multiplication of 64-bit operands, optionally negate the result, detect 32-bit or 64-bit signed overflow of the result, and return a full 128-bit result. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
85 lines
2.6 KiB
VHDL
85 lines
2.6 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.common.all;
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entity multiply is
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generic (
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PIPELINE_DEPTH : natural := 4
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);
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port (
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clk : in std_logic;
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m_in : in Execute1ToMultiplyType;
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m_out : out MultiplyToExecute1Type
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);
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end entity multiply;
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architecture behaviour of multiply is
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signal m: Execute1ToMultiplyType := Execute1ToMultiplyInit;
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type multiply_pipeline_stage is record
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valid : std_ulogic;
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data : unsigned(127 downto 0);
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is_32bit : std_ulogic;
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neg_res : std_ulogic;
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end record;
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constant MultiplyPipelineStageInit : multiply_pipeline_stage := (valid => '0',
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is_32bit => '0', neg_res => '0',
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data => (others => '0'));
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type multiply_pipeline_type is array(0 to PIPELINE_DEPTH-1) of multiply_pipeline_stage;
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constant MultiplyPipelineInit : multiply_pipeline_type := (others => MultiplyPipelineStageInit);
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type reg_type is record
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multiply_pipeline : multiply_pipeline_type;
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end record;
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signal r, rin : reg_type := (multiply_pipeline => MultiplyPipelineInit);
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begin
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multiply_0: process(clk)
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begin
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if rising_edge(clk) then
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m <= m_in;
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r <= rin;
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end if;
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end process;
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multiply_1: process(all)
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variable v : reg_type;
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variable d : std_ulogic_vector(127 downto 0);
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variable d2 : std_ulogic_vector(63 downto 0);
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variable ov : std_ulogic;
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begin
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v.multiply_pipeline(0).valid := m.valid;
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v.multiply_pipeline(0).data := unsigned(m.data1) * unsigned(m.data2);
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v.multiply_pipeline(0).is_32bit := m.is_32bit;
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v.multiply_pipeline(0).neg_res := m.neg_result;
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loop_0: for i in 1 to PIPELINE_DEPTH-1 loop
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v.multiply_pipeline(i) := r.multiply_pipeline(i-1);
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end loop;
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if v.multiply_pipeline(PIPELINE_DEPTH-1).neg_res = '0' then
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d := std_ulogic_vector(v.multiply_pipeline(PIPELINE_DEPTH-1).data);
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else
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d := std_ulogic_vector(- signed(v.multiply_pipeline(PIPELINE_DEPTH-1).data));
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end if;
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ov := '0';
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if v.multiply_pipeline(PIPELINE_DEPTH-1).is_32bit = '1' then
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ov := (or d(63 downto 31)) and not (and d(63 downto 31));
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else
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ov := (or d(127 downto 63)) and not (and d(127 downto 63));
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end if;
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m_out.result <= d;
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m_out.overflow <= ov;
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m_out.valid <= v.multiply_pipeline(PIPELINE_DEPTH-1).valid;
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rin <= v;
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end process;
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end architecture behaviour;
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