Benjamin Herrenschmidt bedc9c0085 litedram: l2: Add a few comments about litedram behaviour ...

litedram ignores a couple of signals of his "pseudo-axi" port,
this adds a bit of documentation around it.

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

2020-07-08 17:27:32 +10:00

..

fusesoc-add-files.py

litedram: Remove old "VexRiscV" based initializations

2020-06-05 11:23:04 +10:00

litedram-wrapper-l2.vhdl

litedram: l2: Add a few comments about litedram behaviour

2020-07-08 17:27:32 +10:00

sim_dram_verilate.mk

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

sim_litedram_c.cpp

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

sim_litedram.vhdl

litedram: Add simulation support

2020-06-05 10:24:47 +10:00

wave_tb.gtkw

litedram: l2: Latency improvements

2020-07-08 16:47:30 +10:00

wave.gtkw

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00

wave.opt

litedram: Add an L2 cache with store queue

2020-06-05 10:33:27 +10:00